Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[inf64]

So 10-15% bigger, and likely 10-15% better IPC (I think that RWC is ahead of Zen 4?). If so, that seems fine.

Edit: Actually if Lion Cove now is physically missing AVX-512, I would expect a bigger uplift, though again Zen 5 IPC numbers include some AVX 512 workloads, so comparison outside AVX 512 is not clear.

Edit2: Raptor Cove is only around 1-5% ahead of Zen 4 according to Spec 2017. Not sure what Zen 5 uplift is outside of AVX 512, so hard to compare to Lion Cove in lunar lake.

Raptor cove is around 2-3% faster than Zen 4, while RWC is around ~3% slower than Raptor cove (so RWC and Zen 4 are ~even). Zen 5 should end up having a slight edge over Lion Cove if both IPC projections are confirmed in reality. In AVX512 optimized stuff Zen 5 should have a big advantage though.

 

[dullard]

Double Post

 

[FlameTail]

Well yeah e-core team if they truly are progressing as good as this, should just replace the P core team and one unified core type again and bye bye hybrid arch and back to same type of core as only reason hybrid came about is because Intel P core team had cores too large and power hungry to get as many as AMD in a consumer sized socket at reasonable power draw and they needed the quantity of much weaker e-cores to be competitive in perfect parallel workloads with AMD. Otherwise Big.Little does not exist in desktop.

Conroe moment maybe in a few years and e-core team should replace P core team if things are truly progressing as rumored form e-core team?

Intel will still need an Apple-style E-core. An E-core that prioritises power efficiency above all else. This is for their laptop chips though. Desktop can use one core type.

 

[SiliconFly]

I mean, you just gave a textbook justification of hybrid architecture. You didnt really address the point of my post though. Sorry to keep bringing up AMD in an Intel thread, but they are able to put 16 big cores into a chip and still have excellent performance and power consumption. I guess what I am trying to say, is that Lion Cove still seems behind in performance and/or power consumption, or they would not have to bother with the E cores. It is also disappointing that Lunar Lake and the most performant Arrow Lake are on a TSMC node. What happened to process leadership? I though 20A was supposed to bring leadership. Are we depending on 18A now? And if it is simply a matter of supply, I dont consider a process leading edge if it cant provide sufficient wafers with adequate yields to satisfy production demands.

Process leadership is 2025.

 

[invisible_city]

Process leadership is 2025.

Can’t wait. Finally competition is returning. AMD has been stagnating with the lack of it. No core count progression, niche improvements focused on trendy AI crap. I’m running a Zen 3 still because all the new stuff is mid. Looking forward to upgrading to 32 core chadmont_dark + lion_cove_next_brad or zen 6 32c

 

[SiliconFly]

Thanks, you didn't disappoint with your "useful" reply as always.

So once more, why did they choose 4+4 config instead of 2+8 for example, which would be comparable in size If not a bit smaller.

Lion Cove is for max ST performance and responsiveness, so It's understandable, to use them, but why 4, when this is intended for ultrabooks with a limited TDP?
Skymont cluster offers better perf/W than a Lion Cove cluster and is also a lot smaller, 2 of them would provide significantly higher performance than a single Lion Cove cluster.


Why can't there be 3 clusters? One with 2 P-cores and 2 clusters with 4 E-cores each?
And Intel could keep active only a single E-core cluster.

P cores still the main cores. E cores kick in only when the s/w threads don't require that much performance and/or idling a bit. E cores are still "crutches" or just "helper" cores to the main P cores, cos ST perf is still the most important factor when it comes to performance.

Even in basic tasks like web browsing, ST perf is still very crucial.

 

[SiliconFly]

Can’t wait. Finally competition is returning. AMD has been stagnating with the lack of it. No core count progression, niche improvements focused on trendy AI crap. I’m running a Zen 3 still because all the new stuff is mid. Looking forward to upgrading to 32 core chadmont_dark + lion_cove_next_brad or zen 6 32c

Zen6 is supposed to be a big leap if rumors are right.

 

[Hulk]

What structures in a CPU are generally referred to as being in the "front end" and which ones are in the "back end?"

 

[lightisgood]

In AVX512 optimized stuff Zen 5 should have a big advantage though.

I had read this writing in the review of Rocket Lake, 2021 and feel an irony of history now...

 

[Hitman928]

Raptor cove is around 2-3% faster than Zen 4, while RWC is around ~3% slower than Raptor cove (so RWC and Zen 4 are ~even). Zen 5 should end up having a slight edge over Lion Cove if both IPC projections are confirmed in reality. In AVX512 optimized stuff Zen 5 should have a big advantage though.

Raptor cove is slightly behind Zen 4 in IPC according to Anandtech’s SPEC results. RWC may have a slight IPC regression, there’s conflicting data on that. If we assume Intel and AMD IPC numbers for next gen exactly match SPEC, then Zen 5 should be ahead in IPC by like 7% or so. Close enough that it shouldn’t matter much in a generalized performance way.

 

[lightisgood]

Raptor cove is slightly behind Zen 4 in IPC according to Anandtech’s SPEC results. RWC may have a slight IPC regression, there’s conflicting data on that. If we assume Intel and AMD IPC numbers for next gen exactly match SPEC, then Zen 5 should be ahead in IPC by like 7% or so. Close enough that it shouldn’t matter much in a generalized performance way.

Could you tell me why you are only thinking about SPEC CPU?
GB5, GB6, PCmark and so on are major benchmark, today.
Besides, Lisa avoided cleverly telling about Zen 5's SPECint score...

 

[SiliconFly]

This matches what Exist has said for years, including that P Core tried to kill E core team and also others Cores projects at Intel. And that they were very adversarial against Jim Keller while the E core team was very helpful and accepted his guidance.

Like I always say, it's time for the fat/power hungry P cores to die.

 

[SiliconFly]

I will predict the real highlight of the E core team will come with Arctic Wolf - the next big gain, with another 30% gain.

If the decline is to be expected, then it'll be after Arctic Wolf, just as Sandy Bridge was peak for IDC.

The fact that such a small core can perform that close to the P cores is a big suggestion that x64 cores have a long way to go. We will see if they manage to overcome ARM again.

Ditto.

 

[Hitman928]

Could you tell me why you are only thinking about SPEC CPU?
GB5, GB6, PCmark and so on are major benchmark, today.
Besides, Lisa avoided cleverly telling about Zen 5's SPECint score...

This has been discussed multiple times in just the past few weeks so I’m not going to rehash it again but in summary, SPEC is the industry standard for generalized benchmark and has been the measuring stick for IPC measurements for generations now.

AMD never includes SPEC in their consumer products announcements.

 

[invisible_city]

I had read this writing in the review of Rocket Lake, 2021 and feel an irony of history now...

Yeah. I don’t understand Intels long term plans here. I currently wish they hadn’t removed support on consumer parts, because I care about
it for ML (I have a 4090, but that’s only
24GB, and CPUs are just easier to work with). But maybe in the next 3 years their plan comes together with the move to NPUs and AVX10?

 

[FlameTail]

This matches what Exist has said for years, including that P Core tried to kill E core team and also others Cores projects at Intel. And that they were very adversarial against Jim Keller while the E core team was very helpful and accepted his guidance.

How does that dude keep making so many good predictions?

 

[lightisgood]

This has been discussed multiple times in just the past few weeks so I’m not going to rehash it again but in summary, SPEC is the industry standard for generalized benchmark and has been the measuring stick for IPC measurements for generations now.

Again, could you tell me why you are ONLY thinking about SPEC CPU?

AMD never includes SPEC in their consumer products announcements.

Okay. That is to say, Turin was not unveiled in Computex 2024.

 

[FlameTail]

Again, could you tell me why you are ONLY thinking about SPEC CPU?

Because SPEC is best.

 

[Hitman928]

Again, could you tell me why you are ONLY thinking about SPEC CPU?

I'm not saying that SPEC is the only benchmark that should ever be considered, but for comparing generalized IPC, it has been the tool used for several generations now. There are multiple reasons for this which I'm not going to rehash because we have recently discussed it for pages already.

Okay. That is to say, Turin was not unveiled in Computex 2024.

I don't understand your point. The only things AMD showed for Turin was HPC and AI related stuff compared to Xeon.

 

[Abwx]

So 10-15% bigger, and likely 10-15% better IPC (I think that RWC is ahead of Zen 4?). If so, that seems fine.

It is not, Computerbase provided a comparison at same frequency, and in all cases excepted CBR20 Zen 4 has better MT IPC than the P cores used in the 12900K, how is this possible if ST IPC was lower by 10%..?..

And before one comes for a theorical better SMT scaling of Zen 4 that s just moot, because 5% better ST IPC cant be compensated in MT by marginaly better SMT yield, let alone with 10% better ST IPC as proven by the estimation below.

If a core has say 100 ST IPC and 30% SMT yield it will perform at 130 in MT.
A core that has just 5% better IPC and only 25% SMT yield is at 131.5 in MT.
Now a core at 110 with only 25% SMT yield would do 137.5.

SMT yields of AMD and Intel are not as far apart as in this exemple, so it s obvious that Intel having better IPC is just an urban legend that doesnt pass the most basic examination, actually it s the contrary.

 

[H433x0n]

Raptor cove is around 2-3% faster than Zen 4, while RWC is around ~3% slower than Raptor cove (so RWC and Zen 4 are ~even). Zen 5 should end up having a slight edge over Lion Cove if both IPC projections are confirmed in reality. In AVX512 optimized stuff Zen 5 should have a big advantage though.

ARL-S P cores are slightly different with more L2$ and HT present (although maybe not enabled).

Based on the disparity of how transparent IPC was calculated for both - I would wait for 3rd party reviews before saying anything conclusively.

 

[lightisgood]

Intels long term plans here.

It is the ultimate goal, client 2.0.

https://images.anandtech.com/doci/16021/Section%208%20%2821%29.jpg

Intel Moving to Chiplets: ‘Client 2.0’ for 7nm

www.anandtech.com

 

[FlameTail]

Lunar Lake has very robust memory subsystem.

8 MB GPU L2.
8 MB SLC.
136 GB/s memory bandwidth.

This is better than M3, X Elite or a certain Strix...

 

[SiliconFly]

Can someone explain further the from the Intel engineers video?

Extended scalability - IP agnostic and partition agnostic

The NoC fabric interconnect now has extended scalability. He says it can now seamlessly connect to different types of PHY layers in different IP blocks thereby making the NoC fabric IP agnostic. As an added bonus, now the IP blocks can be shuffled and shifted from one tile to another very easily (assuming the IP block has the target implementation) which he calls partition agnostic.

For example, let us say the cpu soc has 2 tiles (the cpu tile on N3 & the pc tile on N6). Now, the cpu tile has a media engine IP block to take care of lots of media/transcoding stuff, etc. When the NoC fabric is partition agnostic, we can move the media engine from the N3 cpu tile to the N6 pc tile with very little penalty. The PHY layers of the IP block will now be different due to different transistor characteristics on N3 & N6, but the fabric will ensure a pretty much transparent interconnect.

 

[invisible_city]

Lunar Lake has very robust memory subsystem.

8 MB GPU L2.
8 MB SLC.
136 GB/s memory bandwidth.

This is better than M3, X Elite or a certain Strix...

Memory bw is impressive for 15-17W