Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[poke01]

What is area of the compute tile? 140? Is that fully confirmed?

 

[Wolverine2349]

Some updates from my source:

• the core in ARL is slightly beefier. Beside higher clock speed, L2 cache is 3MB (vs 2.5MB on LNL). The e-core is on the Ringbus, so gets access to L3. Of course, it is still 4-tile design vs 2 tiles of LNL, memory controller is inside the SoC tile.
• Next year, Intel might not launch the 8+32 version of ARL-S. It was in the roadmap before, now no more...
• The reason might be Intel has to increase the TOPS of NPU to 40 due to Microsoft's mandate requirements. My source can't confirm which process new SoC tile is being fabbed.

It is early leaks, I will update if anything new come up.

So wait its a 4 tile design Arrow Lake and not 2? Does this mean not all Lion Cove and Skymont cores are in the same Tile unlike Lunar Lake andd Meteor Lake where they are excpet separate tile in MTL for low power e-core?

Or are all CPU core for Arrow Lake in same tile for best core to core latency?

 

[Ghostsonplanets]

What is area of the compute tile? 140? Is that fully confirmed?

140mm²

https://twitter.com/x/status/1745244534978592784

 

[Ghostsonplanets]

So wait its a 4 tile design Arrow Lake and not 2?

Yes. Arrow Lake inherits the same tile structure as Meteor Lake. GPU tile, SoC tile, Compute tile, IO tile and Foveros 3D base tile. But some of the tiles are updated/tweaked a bit when compared to MTL.

Or are all CPU core for Arrow Lake in same tile for best core to core latency?

Lion Cove and Skymont are all on the same Compute Tile in Arrow Lake. It's the same structure as Meteor Lake Compute Tile.

excpet separate tile in MTL for low power e-core?

There should be no LPE Cores for ARL-S. It's one of the tweaks made to the SoC tile from MTL to ARL-S.

 

[Ghostsonplanets]

Not sure if it was shared, but Nemez did the MTL die annotation:

https://twitter.com/x/status/1794473996370469330

 

[Wolverine2349]

Yes. Arrow Lake inherits the same tile structure as Meteor Lake. GPU tile, SoC tile, Compute tile, IO tile and Foveros 3D base tile. But some of the tiles are updated/tweaked a bit when compared to MTL.

Lion Cove and Skymont are all on the same Compute Tile in Arrow Lake. It's the same structure as Meteor Lake Compute Tile.

There should be no LPE Cores for ARL-S. It's one of the tweaks made to the SoC tile from MTL to ARL-S.

What are the 4 tiles for then?

Is the ring bus with the P and e-cores on a single tile?

And what are the other 3 tiles?

And how does it compare to Raptor Lake and Alder Lake which have a ring bus with P and e-cores and also more?

So is that why latency will be worse with Arrow Lake than Raptor and prior because tiles only have ring bus where as all is on ring in RPL but separated by tiles for IMC and other parts for Arrow Lake?

Kind of like how AMD has a single ring bus in a CCX within a CCD, but they have separate CDs and IO die for infinity fabric and such which is why AMD latency is worse going to than components than Intel Raptor Lake which has all in ring bus?

 

[Ghostsonplanets]

What are the 4 tiles for then?

Because ARL PoR was to reuse MTL tiled structure to cheapen development costs. But MTL went too hard into tiled design and ARL sadly inherit the same structure.

Future generation will use less tiles.

Is the ring bus with the P and e-cores on a single tile?

Yes. It's the same structure as Meteor Lake Compute Tile. Give a look at it.

And what are the other 3 tiles?

The same as I said it: Arc Alchemist 64 XVE GPU Tile, SoC tile and IO tile.

So is that why latency will be worse with Arrow Lake than Raptor and prior because tiles only have ring bus where as all is on ring in RPL but separated by tiles for IMC and other parts for Arrow Lake?

Latency will be higher because compute tile will need to communicate through the IOSF. The example you gave about AMD inter CCX communication latency is a decent one.

 

[Hulk]

I just noticed that the slide showing Skymont outperforming Raptor Cove by 2% in "general software" there is a little note reading "when on the LLC ring."

So Skymonts in LL are not Raptor Coves. But they will be in ARL.

 

[Wolverine2349]

Yes. It's the same structure as Meteor Lake Compute Tile. Give a look at it.

Have looked at it and its core to core latency while not bad is not great either even within same tile and not near as consistent as the core to core latency between P cores and threads in ALder Lake and Raptor Lake and Comet Lake. There is some latency increase going to e-cores though

Where as AMD has excellent and very consistent low latency between cores with a single 8 core CCX. Though the latency is beyond horrible when it exits the CCX but superior within it for AMD.

 

[controlflow]

RWC in GNR has 8 wide decode?

Intel Launches Xeon 6700E "Sierra Forest" CPUs - Initially Up To 144 Cores Review - Phoronix

www.phoronix.com

 

[invisible_city]

RWC in GNR has 8 wide decode?

Intel Launches Xeon 6700E "Sierra Forest" CPUs - Initially Up To 144 Cores Review - Phoronix

www.phoronix.com

View attachment 100630

Good catch!

 

[Tigerick]

Can't they just use the new N4P GPU tile of Arrow Lake H to give the necessary TOPs for ARL-S Refresh next year?

The ARL H IGP tile brings back XMX while also clocking higher. Pretty sure it would be able to match the 40 TOPs requirement easily (Although the problem I think is that Desktop get a 64 XVE iGP while ARL H one is 128 XVE. So that's an area and cost increase either way).

I thought MS's mandate TOPS requirement is reside inside NPU due to battery life concerns. Thus, GPU and CPU's TOPS does not count.

 

[Ghostsonplanets]

I thought MS's mandate TOPS requirement is reside inside NPU due to battery life concerns. Thus, GPU and CPU's TOPS does not count.

Yes. But that's irrelevant for ARL-S, no? Intel can meet the TOPs requirement just fine with the GPU itself as there's no battery life concern in DT. So I don't understand why 8+32 being cancelled might have been something due to pressure of NPU width increase.

Unless it's a byfactor of ARL-H and S sharing the same SoC tile. That would explain a increase in NPU area affecting DT Core configuration plans.

 

[FlameTail]

Fooling around a bit with the compute die shot.

View attachment 100627

Hey. This is great. But the 240 mm² die area figure you used is wrong. Could you relabel the stuff by using the correct die area (140 mm²)?

 

[Hulk]

Hey. This is great. But the 240 mm² die area figure you used is wrong. Could you relabel the stuff by using the correct die area (140 mm²)?

Oh jeez! Okay let me rework that...

 

[Hulk]

 

[lightisgood]

• The reason might be Intel has to increase the TOPS of NPU to 40 due to Microsoft's mandate requirements. My source can't confirm which process new SoC tile is being fabbed.

Thanks. I was just thinking this point.
IMO, the capacity of Intel 3 is mainly filled by Xeon 6.
Granite Rapids-AP has really big tile...
So, ARL's Soc tile should be fabbed by the similar LNL process.

 

[Joe NYC]

Arrow Lake should be around 20% faster than Raptor Cove for single core stuff. That is more than enough to beat Zen 5 in many benchmarks.

I have a hunch hat it will go the other direction. Taking just one variable, memory latency and some round numbers:

MTL P-Core to LNL P-Core = +14%
(given from the presentation)

This transition improves latency since memory controller is on the same die in LNL (and also SLC). Let's say, memory latency improvement buys 4%, then excluding the memory latency improvement, core for core is 10%.

RPL P-Core to ARL P-Core = ?

If we start with core for core improvement of 10%
Going from monolithic RPL to tile based ARL, we lose 4%

Then,
RPL P-Core to ARL P-Core = 10% - 4% = 6% IPC gain

 

[nahiyoahz865910900100@out]

View attachment 100637

much smaller than raptor lake P core and E core, would there be heat density problem for arrow lake laptop HX series?

 

[H433x0n]

I have a hunch hat it will go the other direction. Taking just one variable, memory latency and some round numbers:

MTL P-Core to LNL P-Core = +14%
(given from the presentation)

This transition improves latency since memory controller is on the same die in LNL (and also SLC). Let's say, memory latency improvement buys 4%, then excluding the memory latency improvement, core for core is 10%.

RPL P-Core to ARL P-Core = ?

If we start with core for core improvement of 10%
Going from monolithic RPL to tile based ARL, we lose 4%

Then,
RPL P-Core to ARL P-Core = 10% - 4% = 6% IPC gain

You’re deducting memory latency twice. You’re also ignoring that desktop will have less latency than MTL’s Redwood Cove and LNL from the ability to run higher ring clocks and a desktop oriented SoC tile that doesn’t have to worry about idle power draw and gets rid of things like LP ecores. Finally, there is an additional amount of L2$ for the ARL-S variant of Lion Cove.

It’s a moot point anyway when you consider the competitive environment. It could end up at 0% improvement overall and still be competitive. RPL already had 10-15% 1T advantage in the popular benchmarks to measure client 1T performance. They got completely let off the hook.

 

[Joe NYC]

You’re deducting memory latency twice.

That's correct:

Good -> Good = 0
Bad -> Bad = 0
Bad -> Good = +1 (MTL -> LNL)
Good -> Bad = -1 (RPL -> ARL)

Difference between (Bad -> Good) - (Good -> Bad) = 1 - (-1) = 2

You’re also ignoring that desktop will have less latency than MTL’s Redwood Cove and LNL from the ability to run higher ring clocks and a desktop oriented SoC tile that doesn’t have to worry about idle power draw and gets rid of things like LP ecores. Finally, there is an additional amount of L2$ for the ARL-S variant of Lion Cove.

It’s a moot point anyway when you consider the competitive environment. It could end up at 0% improvement overall and still be competitive. RPL already had 10-15% 1T advantage in the popular benchmarks to measure client 1T performance.

Clearly, there are other variable, but my point was to analyze only 1 of many variables.
Also, only looking only at Intel side, at 2 transitions of Intel processors. Not looking at AMD.

 

[SiliconFly]

If you're familiar with mobile phones SoC, you might have heard of Memory Side Cache as SLC (System Level Cache) or LLC (Last Level Cache).

It's basically a buffer cache structure in-between the last level of cache of the CPU and the memory dram to avoid unnecessary dram requests and reduce energy, while also providing a increase in available bandwidth.

On Lunar Lake, the CPU and NPU can make usage of it. The Xe² GPU doesn’t because by itself it has a L2 cache of 8MB.

Actually, one of the lunar lake lead architects mentioned that the GPU also has access to Memory Side Cache (but doesn't have much priority like E core cluster).

 

[Hulk]

Actually, one of the lunar lake lead architects mentioned that the GPU also has access to Memory Side Cache (but doesn't have much priority like E core cluster).

Is the memory side cache the 8MB "mystery cache?"

 

[del42sa]

Is the memory side cache the 8MB "mystery cache?"

yes, indeed

 

[SiliconFly]

Is the memory side cache the 8MB "mystery cache?"

Yep. And iirc, it's connected to the P core cluster, E core cluster, GPU, NPU, etc. But priority is mainly for E core cluster as it lacks L3.