Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Wolverine2349]

https://twitter.com/x/status/1799525678032838797

Skymont 4.5ghz to 5ghz clocks ?🤔..

OMG I am so excited if true and 5GHz Skymont all core and Skymont also has the low latency of Raptor Cove and equal performance as Raptor Cove (HT disabled) across all workloads. My dream more than 8 strong cores for a homogenous non-hybrid arch on a single tile/ring bus/ CCX-CCD/die will be here in October.

Can just buy a Core Ultra 275K or 285K and have and disable Lion Cove cores and have a 12-16 all P core 5GHz Raptor Lake equivalent with HT disabled!!!! Here is to hoping!!

 

[SiliconFly]

It’s 10% core area, probably not including L2 which means it ends up being like 0.3% of the compute die area for each of the four P-cores in LNL.

Die area comparison between Lion Cove & Skymont is roughly 1:3 (without $). That means for every 10% area reduction in LNC with HT structures eliminated, represents roughly ~30% die area of Skymont. In other words, in a desktop part with 8 LNC cores, if we disable HT completely, we can easily have 2 additional Skymont cores for the die area saved. This additional 2 Skymont cores can easily give more performance than having HT.

HT is a dinosaur thats refusing to die. Hope there's a way to force kill it.

... that perform at best like 1/3rd the speed of the 16...

15 to 20% at best.

...not including HT was the better option for whatever power envelope Intel was targeting...

I didn't realise that HT is a power hog until the P core designed said so.

It's incredible，5G?

...5GHz Skymont all core... ...Here is to hoping!!...

I think those are more of theoretical limits. Real world SKT boost frequency should be in 4.xGHz range. I maybe totally wrong though.

 

[Hitman928]

Die area comparison between Lion Cove & Skymont is roughly 1:3 (without $). That means for every 10% area reduction in LNC with HT structures eliminated, represents roughly ~30% die area of Skymont. In other words, in a desktop part with 8 LNC cores, if we disable HT completely, we can easily have 2 additional Skymont cores for the die area saved. This additional 2 Skymont cores can easily give more performance than having HT.

Skymont is much closer to a 1:2 ratio with LNC.

HT is a dinosaur thats refusing to die. Hope there's a way to force kill it.

It still has its place for some server needs. Also, lower core count consumer CPUs can still greatly benefit from it. Overall, I'd kind of like to see it go away as well, but it is still useful for most consumers as long as Intel and AMD sell products with <= 6 cores.

 

[Nothingness]

~10% die area is committed to HT? That's hard to believe. Also the extra power consumption only occurs when the HT core is forced to handle two threads, no?

It's not impossible that it's10% (excluding caches area). I guess (I have no experience in that domain) if you want your second thread to perform well, while not sacrificing single thread performance, you have to increase some structures. And these structures can't be clock gated (and even less power gated) as they are the same as for ST, which means they will consume power.

 

[SiliconFly]

Skymont is much closer to a 1:2 ratio with LNC.

Die shot comparison without cache puts it at 1:3. There were 2 different posts on twitter a while ago. And both showed close to 1:3. The second one (i don't have link) nailed it down to an exact 1:3.0x which was a revised figure actually. The most accurate i've come across.

It still has its place for some server needs. Also, lower core count consumer CPUs can still greatly benefit from it. Overall, I'd kind of like to see it go away as well, but it is still useful for most consumers as long as Intel and AMD sell products with <= 6 cores.

HT is awesome for servers. But not for clients. True it's beneficial for lower core count parts. But in this day and age, if anyone is buying quad core, they should be put in one of those cia blacksite prisons. I'll cover the transportation costs. Pinky swear.

To be more precise, Intel should just kill of HT in 6+8 & 8+16 & similar parts... and should try to increase E core counts instead with the saved die area.

 

[Hitman928]

Die shot comparison without cache puts it at 1:3. There were 2 different posts on twitter a while ago. And both showed close to 1:3. The second one (i don't have link) nailed it down to an exact 1:3.0x which was a revised figure actually. The most accurate i've come across.


HT is awesome for servers. But not for clients. True it's beneficial for lower core count parts. But in this day and age, if anyone is buying quad core, they should be put in one of those cia blacksite prisons. I'll cover the transportation costs. Pinky swear.

To be more precise, Intel should just kill of HT in 6+8 & 8+16 & similar parts... and should try to increase E core counts instead with the saved die area.

Do you have a link to the area estimates? The L2 area of the LNC cores aren't as clear to me based on the image Intel put out.

Edit: To add, in LNL, the P-cores have 2.5 MB of cache each while the E-cores have 4 MB shared (I included 1 MB worth per die in the area comparison). That makes me doubt that the E-core to P-core ratio shrinks when excluding L2 cache. Most likely, the 1:3 comparison was including L2 in the P-cores but excluding it in the E-cores. That would get you to about a 1:3 ratio but isn't a valid comparison.

 

[CouncilorIrissa]

HT is awesome for servers. But not for clients. True it's beneficial for lower core count parts. But in this day and age, if anyone is buying quad core, they should be put in one of those cia blacksite prisons. I'll cover the transportation costs. Pinky swear.

You do realise that there are countries where a 6-core SKU costs more than monthly median income, right?

 

[SiliconFly]

Do you have a link to the area estimates? The L2 area of the LNC cores aren't as clear to me based on the image Intel put out.

Edit: To add, in LNL, the P-cores have 2.5 MB of cache each while the E-cores have 4 MB shared (I included 1 MB worth per die in the area comparison). That makes me doubt that the E-core to P-core ratio shrinks when excluding L2 cache. Most likely, the 1:3 comparison was including L2 in the P-cores but excluding it in the E-cores. That would get you to about a 1:3 ratio but isn't a valid comparison.

The comparison had it very clearly labelled. LNC vs SKT both with cache. And then LNC vs SKT both without cache. The first one was a bit rough due to some issues with the images i guess. The second one has better comparisons with hi res images and more accurate/revised results which put it at 1:3 exact (without cache for both).

I tried to locate it for a while without much success. But will keep trying...

You do realise that there are countries where a 6-core SKU costs more than monthly median income, right?

Six cores are kinda okay-ish. But quad cores? Oh god!

 

[invisible_city]

You do realise that there are countries where a 6-core SKU costs more than monthly median income, right?

Yeah we’re very western country oriented here. Rest of world matters too. In any case, I would strongly prefer that Intel gets back to driving consumer performance since AMD is no longer interested. The path forward for that seems Chadmont spam.

 

[Wolverine2349]

Do you have a link to the area estimates? The L2 area of the LNC cores aren't as clear to me based on the image Intel put out.

Edit: To add, in LNL, the P-cores have 2.5 MB of cache each while the E-cores have 4 MB shared (I included 1 MB worth per die in the area comparison). That makes me doubt that the E-core to P-core ratio shrinks when excluding L2 cache. Most likely, the 1:3 comparison was including L2 in the P-cores but excluding it in the E-cores. That would get you to about a 1:3 ratio but isn't a valid comparison.

I had forgotten about that the L2 cache. Then my hopes of a buying a Core Ultra 275K or 285K and disabling P cores and having an all Skymont core 12-16 P core Raptor Lake equivalent for homogenous non-hybrid arch CPU probably not reality.

Shared 4MB L2 per 4 e-core cluster where each P core has 2.5MB. So e-cores latency will be crippled.

Kind of like how Zen 4C has equal IPC to Zen 4 and Zen 5C will have equal IPC to Zen 5, but much less cache and clocks so real world performance across the board not near as good.

Oh well my hopes probably dashed for this Fall.

But Intel could put maybe more L2 cache per Skymont core on a dedicated die without clusters for better latency if they were intended to be Raptor Cove replacement in all work loads. But unfortunately at least their design initially they are intended for hybrid arch not to be on their own yet,

Though long term Intel can use these better cores and tune them and make them the new P cores. But unfortunately unlikely they can make that design for the great latency and L2 changes by this Fall.

 

[SiliconFly]

Considering all the changes/upgrades LNC has received over previous uarchs, none of them seem to standout (performance wise). There are no killer upgrades that are awe-inspiring. Will LNC bring in enough ST perf uplift in ARL? Hard to say at this point. And all the info published by the Intel P core team aren't inspiring either.

Has Intel's P core hit it's evolutionary limit? Should Intel just axe the Israel Design Center?

 

[The Hardcard]

I had forgotten about that the L2 cache. Then my hopes of a buying a Core Ultra 275K or 285K and disabling P cores and having an all Skymont core 12-16 P core Raptor Lake equivalent for homogenous non-hybrid arch CPU probably not reality.

Shared 4MB L2 per 4 e-core cluster where each P core has 2.5MB. So e-cores latency will be crippled.

Kind of like how Zen 4C has equal IPC to Zen 4 and Zen 5C will have equal IPC to Zen 5, but much less cache and clocks so real world performance across the board not near as good.

Oh well my hopes probably dashed for this Fall.

But Intel could put maybe more L2 cache per Skymont core on a dedicated die without clusters for better latency if they were intended to be Raptor Cove replacement in all work loads. But unfortunately at least their design initially they are intended for hybrid arch not to be on their own yet,

Though long term Intel can use these better cores and tune them and make them the new P cores. But unfortunately unlikely they can make that design for the great latency and L2 changes by this Fall.

i’m not clear why you would want to disable the P cores. In addition to building an effective E core, this generation appears to be fixing all the previous scheduling issues between P and E.

if Intel has its act together even half as much as it appears to, you gain virtually zero by disabling cores.

 

[hemedans]

You do realise that there are countries where a 6-core SKU costs more than monthly median income, right?

Most lowend from Intel nowadays have plenty of cores, re imagine i3 1215U without HT and Skymont, there won't be any issue.

 

[SiliconFly]

i’m not clear why you would want to disable the P cores. In addition to building an effective E core, this generation appears to be fixing all the previous scheduling issues between P and E.

if Intel has its act together even half as much as it appears to, you gain virtually zero by disabling cores.

For example, take ARL-H 6P+8E. The Skymont cores are connected to L3 which offers more performance than the ones in Lunar Lake. And if we take only the performance of those 8 E cores (with the 6 P cores disabled), thats more than sufficient performance for a lot of people for day-to-day usage. Additionally we get a mind-boggling added bonus of extreme battery life. Probably upto 48 hours of casual use. Just sayin'.

Sadly, the LNC P cores aren't what many expected it to be.

 

[invisible_city]

For example, take ARL-H 6P+8E. The Skymont cores are connected to L3 which offers more performance than the ones in Lunar Lake. And if we take only the performance of those 8 E cores (with the 6 P cores disabled), thats more than sufficient performance for a lot of people for day-to-day usage. Additionally we get a mind-boggling added bonus of extreme battery life. Probably upto 48 hours of casual use. Just sayin'.

Sadly, the LNC P cores aren't what many expected it to be.

We’ll see how lnc performs in arrow lake

 

[eek2121]

Does anyone know when we are actually getting some sku's? These things must be many months away if we don't even have that.

Arrow Lake or Lunar Lake? Lunar Lake should begin showing up in September. Arrow Lake won't realistically be available before 2025. Some speculate that Arrow Lake will launch at CES, but unless Intel really has knocked one out of the park with it (possibility), it will likely "launch" in Q4 with decent availability in 2025.

No Intel chip designers have explicitly stated that LNC in ARL will have HT. Some of the things they said kinda implies that ARL may get HT. Even I think it will. But Intel hasn't confirmed it yet.

And about HT, the P core designer said it in very high clarity the same thing I've been saying all along. HT kicks in and gives the performance increase only after all physical cores gets fully saturated during heavy multi-threaded workloads. And imho, this situation is not useful for most consumers and completely useless when there are plenty of E cores. HT is archaic and should just die.


4.6GHz is the best leak we've had till now.


In a month or two since they're targeting a sep launch.

They have, just not on the record. We can agree to disagree, however, and we'll find out soon at any rate.

They've been playing with some really interesting stuff (including things not mentioned here/in their videos) and it actually kind of makes me want to get back into hardware design/development (AMD and other companies avoiding CMT is another reason, almost completely unexplored area IMO). That is the thing that really kills me with ALL tech companies. Get rid of the corporate nonsense and you see some amazing and talented engineers behind it all. The corporate attitude limits that talent in many different ways, and even things like big wins in the engineering department can be completely hidden by corpspeak, especially for publicly traded companies

NOTE that if you ever did want to get into chip design, it is super cheap (and 'relatively' accessible assuming you can learn the foundational stuff). Forget 7nm/5nm/3nm/2nm, you can build stuff on much older processes for super cheap...I even remember a guy building a fab in his garage (something like 10um, a far cry from Intel 18a, but still). You can even breadboard a really basic chip, and it is a lot of fun. I can provide recommendations if you need a place to get started.

 

[SiliconFly]

Arrow Lake or Lunar Lake? Lunar Lake should begin showing up in September. Arrow Lake won't realistically be available before 2025. Some speculate that Arrow Lake will launch at CES, but unless Intel really has knocked one out of the park with it (possibility), it will likely "launch" in Q4 with decent availability in 2025.

They have, just not on the record. We can agree to disagree, however, and we'll find out soon at any rate.

They've been playing with some really interesting stuff (including things not mentioned here/in their videos) and it actually kind of makes me want to get back into hardware design/development (AMD and other companies avoiding CMT is another reason, almost completely unexplored area IMO). That is the thing that really kills me with ALL tech companies. Get rid of the corporate nonsense and you see some amazing and talented engineers behind it all. The corporate attitude limits that talent in many different ways, and even things like big wins in the engineering department can be completely hidden by corpspeak, especially for publicly traded companies

NOTE that if you ever did want to get into chip design, it is super cheap (and 'relatively' accessible assuming you can learn the foundational stuff). Forget 7nm/5nm/3nm/2nm, you can build stuff on much older processes for super cheap...I even remember a guy building a fab in his garage (something like 10um, a far cry from Intel 18a, but still). You can even breadboard a really basic chip, and it is a lot of fun. I can provide recommendations if you need a place to get started.

I used to play around with microprocessors & micro-controllers in the early days. 8051 was my favorite. Even made a 80386DX addon board for a h/w based debugger. Good old times. And I think you're talking about tiny tapeout.

 

[Wolverine2349]

i’m not clear why you would want to disable the P cores. In addition to building an effective E core, this generation appears to be fixing all the previous scheduling issues between P and E.

if Intel has its act together even half as much as it appears to, you gain virtually zero by disabling cores.

Well is every issue perfect even with WIN10. It's still heterogeneous arch and can all game software be accounted for?

Isn't some software still not play nice with heterogeneous arch?

Supposedly every issue was fixed with 13th and 14th Gen scheduling yet Star Citizen and Elden Ring and some Wong game had issues.

I want best Raptor Lake 12 to 16 all P core equivalent homogeneous arch on single die for best set and forget gaming solution of all games all types past 15 to 20 years and furure games as well.

Will heterogeneous arch with Arrow Lake provide that unlike 13th and 14th Gen?

 

[DrMrLordX]

Based on LNL's design philosophy, if there is busy Lion Cove frequently, that is no less than a waste of power consumption.
Intel dosen't aim at squeezing LNC performance from the start.

That's orthagonal to what we're discussing. Lunar Lake can shut down the entire P-core "island" whether or not it has HT. HT would only come into play in intensive tasks that utilize more than eight threads.

Why is it hard to believe?

Based on everything I've ever heard from people "in the know" about HT in the past. Plus now that I've owned a few SMT CPUs (granted, they've all been AMD CPUs) it's hard to believe that baseline power consumption for a core would go up measurably in a 1T scenario.

It’s 10% core area, probably not including L2 which means it ends up being like 0.3% of the compute die area for each of the four P-cores in LNL.

That makes a little more sense. But the last time it was described to me what SMT required from core area, it didn't seem like a huge deal.

 

[SiliconFly]

That makes a little more sense. But the last time it was described to me what SMT required from core area, it didn't seem like a huge deal.

The Intel P core designer stated clearly that if the HT structures are physically present in LNC and enabled, it uses more power. Thats one of the key reasons, LNC doesn't include HT in LNC. I think in LNL, LNC doesn't even include the HT related transistors.

 

[Hulk]

14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed, unless it's all a big lie akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package, fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it, but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info, but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally powerful cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.

 

[Thunder 57]

14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed unless it's all a big like akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally power cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.

Well put. Much more interesting times these days in the CPU world than GPU world.

 

[DAPUNISHER]

Excellent discussion going on here. Props to everyone participating. I learn from you all constantly. And I hate to interrupt the flow, but I need to make a quick FYI for all of the new members and visitors.

You can call yourself fanboy, because that is not flame bait. Putting this out there for any that might be confused why warnings and infractions are issued for using that type of language but not on Hulk's post.

Mod DAPUNISHER.

 

[invisible_city]

14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed unless it's all a big like akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally power cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.

Well put. Both companies are doing amazing work. Glad to see Intel back (provided they deliver what the promised in September)

 

[DrMrLordX]

The Intel P core designer stated clearly that if the HT structures are physically present in LNC and enabled, it uses more power.

It'd be interesting to see what that power delta is in "real world" usage scenarios. The e-cores should be solely engaged often enough that it seems like P-cores having HT wouldn't be a big issue. But I could be very wrong.

Thats one of the key reasons, LNC doesn't include HT in LNC. I think in LNL, LNC doesn't even include the HT related transistors.

Does that mean that Arrow Lake-S will include those transistors?