Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Hans Gruber]

Those clocks at ~170W TDP? AFAIK this was the last info we had on power limits for ARL. I would argue that power and thermals will be very important towards establishing a MT winner.

Personally I favor ARL for the MT win simply because of the core count and the switch to TSMC, but I would not venture to guess a delta at this stage. Simply punching in IPC uplifts and max clocks (or close to max) will not get us far this time around.


People are rightfully excited about Skymont because it shows a clear path forward for Intel even if the P core design team stumbles. That being said, when compared with the dense variant of Zen 5, Skymont won't have any meaningful advantage, at least not one we can readily identify today. The term "Conroe moment" has been so diluted on this forum that I'm starting to think all it means is "well done CPU arch". There's no leapfrogging, the competition is right next to them offering a very strong package in the same time frame.

Execution consistency from now on is still the most important metric that should be used to judge Intel, a strong architectural uplift like Skymont is just an enable. (the same applies for AMD, but not the place for them here)

You are missing one key point. Since Zen 5 will not be on 3nm. Arrow Lake may be as efficient if not more than Zen 5. That may come as a complete shock to forum members here. The uplift from going from 10nm to 20A (5nm) may bring a significant uplift in performance beyond IPC gains. The omission of hyperthreading is offset by the enhanced e core assortment. Historically, Intel has never struggled to get impressive IPC gains when needed.

Intel said it would not be until 18A that they would have a silicon advantage over TSMC. This was many months ago and the assumption was that Zen 5 would be on 3nm. Intel has said 18A would be 10% more efficient than 20A. For that reason alone, it's good that AMD is releasing Zen 5 in July.

Arrow Lake should be compared to the Alder Lake release. A new process package and new silicon at the time 10nm. People here act as if Arrow Lake is a revision of Raptor Lake. A lot of people deny that Alder Lake was really good architecture with bad silicon compared to TSMC. Later this year they will have much better silicon and it seems like deer in the headlights for some. That's why some have said it may be another Conroe moment. The fact that 18A is the next step fairly quickly (late 2025). Intel was on 14nm for more than 6 years. Now they are planning two significant node shrinks in a year.

That's why I said in previous posts that AMD would have to have a Zen 5+ which would have to be on N3E (3nm) or similar silicon. It's not only about a performance uplift but an efficiency uplift that will make AMD relevant with 18A around the corner.

Let's assume Arrow Lake (20A) has an 18% IPC gain. If there is a performance uplift of 10% from the silicon in addition to the 18% IPC gain. We would be looking at a 28% clock for clock gain over Raptor Lake. Even if the performance uplift was 5%, that's still over 20% performance gains over Raptor Lake. I get the 18% IPC gain from what was published for Alder Lake.

If AMD goes cheap on Zen 5 silicon and goes with N4. It's highly likely that Arrow Lake may be more efficient than Zen 5. Nobody on this forum sees that coming but me. I know people are hoping Zen 5 shows up on N4X. N4P is one step down from N4X. It will be interesting to see how Turin (3nm) fares against the Intel 20A server chips in power and efficiency.

 

[Abwx]

Raptor Cove already has like a 7% IPC advantage over Zen 4.

With assumptions like this you wont go very far in your estimations, actually that s the other way round.

If RPC had such an advantage a 8C/16T 7700 would lose all MT benches against a 8P/16T@220W from Intel, yet the 8 P cores of a 12900K are behind a 7700 despite a higher frequency, and as already demonstrated a 20% better SMT scaling (1.3x vs 1.25x) cant compensate for just 5% worse IPC, let alone a 7% difference and with a lower SMT yield difference.

Edit : You can check on the MT charts, click + 114 Eintrage, the 12900K with e cores disabled is referenced Core i9-12900K ohne E-Cores.

Intel Core i9-14900KS im Test: Anwendungs-Benchmarks, Leistungsaufnahme & Temperatur

Intel Core i9-14900KS im Test: Anwendungs-Benchmarks, Leistungsaufnahme & Temperatur / Testsystem und Testmethodik für Anwendungen

www.computerbase.de

 

[Wolverine2349]

With assumptions like this you wont go very far in your estimations, actually that s the other way round.

If RPC had such an advantage a 8C/16T 7700 would lose all MT benches against a 8P/16T@220W from Intel, yet the 8 P cores of a 12900K are behind a 7700 despite a higher frequency, and as already demonstrated a 20% better SMT scaling (1.3x vs 1.25x) cant compensate for just 5% worse IPC, let alone a 7% difference and with a lower SMT yield difference.

Edit : You can check on the MT charts, click + 114 Eintrage, the 12900K with e cores disabled is referenced Core i9-12900K ohne E-Cores.

Intel Core i9-14900KS im Test: Anwendungs-Benchmarks, Leistungsaufnahme & Temperatur

Intel Core i9-14900KS im Test: Anwendungs-Benchmarks, Leistungsaufnahme & Temperatur / Testsystem und Testmethodik für Anwendungen

www.computerbase.de

12900K 12th Gen is Golden Cove. 13th and 14th Gen are Raptor Cove P cores. Raptor Cove has like 5-7% better IPC than Golden Cove. And even Golden Cove clock normalized in Cinebench R23 has a slight lead over Zen 4 in Cinebench R23 by like 2 to 3%?

But Raptor Cove and 13th and 14th Gen while performant stable it is not. They degrade fast and have random stability issues.

 

[Joe NYC]

Well based on info if Arrow Lake new leaks turn out to be as good as suggested and Lion Cove has much better IPC gain than expected and power consumption is reduced.

In that case I suppose Intel could beat AMD handily, though certainly not Conroe level moment.

I mean Zen 5 IPC uplift and more importantly real world performance appears underwhelming (with no clock speed bump_ and Raptor Cove already has like a 7% IPC advantage over Zen 4. If Lion Cove can achieve 20% IPC uplift over Raptor Cove and clocks can be similar, Intel could have a decent sized advantage and maybe closer to equal power consumption or only a little more? Maybe a 15% IPC advantage over Zen 5 and at similar clocks a 15% edge in single thread?

Though in gaming AMD has the X3D and as games love cache and that is games IPC, maybe AMD ties there but Intel maintains advantage by being equal in gaming to X3D and superior in other single thread things and better latency overall and better all around chip.

The above could you see happening? Certainly not the Conroe knockout moment as Conroe had even bigger IPC lead, faster clocks and much lower power consumption something of which all would not happen in above scenario.

Though could Intel deliver a single thread IPC knockout with Lion Cove over Zen 5 kind of like Golden Cove had 15% IPC over Zen 3? Difference being no or much less clock speed advantage but instead of much higher power draw as with Golden Cove to Zen 3, Lion Cove has similar power draw to Zen 5 or only marginally higher with 15% all around better IPC?

Could you see Arrow Lake being that good to have that advantage?

People are making assumptions that Lunar Lake and Arrow Lake will deliver roughly same performance uplift from their predecessors (adjusted for core counts).

I don't agree with this assumption. In my opinion, Lunar Lake will overperform and Arrow Lake will underperform. Arrow Lake will have lower IPC uplift and between 5% and 9% clock speed regression (depending on whether you are starting from 6.0 GHz or 6.2 GHz), while Lunar Lake will have the advertised IPC uplift and no clock speed regression.

 

[CouncilorIrissa]

12900K 12th Gen is Golden Cove. 13th and 14th Gen are Raptor Cove P cores. Raptor Cove has like 5-7% better IPC than Golden Cove. And even Golden Cove clock normalized in Cinebench R23 has a slight lead over Zen 4 in Cinebench R23 by like 2 to 3%?

The difference is much smaller than that. RPC is 2-3% faster than GLC in SPEC.
Let's use benchmarks that actually matter.



edit: It's bloody stupid to use Cinebench as a proxy for general purpose performance as it's basically tests CPU performance at one particular renderer that isn't even ran on CPUs half the time.

 

[Abwx]

12900K 12th Gen is Golden Cove. 13th and 14th Gen are Raptor Cove P cores. Raptor Cove has like 5-7% better IPC than Golden Cove. And even Golden Cove clock normalized in Cinebench R23 has a slight lead over Zen 4 in Cinebench R23 by like 2 to 3%?

Cinebench is an exception, in any other any bench Zen 4 is faster clock/clock, the average is 5.2% better IPC than Golden cove in a 8C/16T comparison, Spec is one thing and softwares we might use are another thing.

Dunno if RPC brought as much as 5-7% improvement, that seems far stretched, guess that most improvement was in frequency and that there were confusions with actual IPC.

And as said a 5% better IPC with 1.25x SMT scaling cant be compensated by even 1.30x better SMT scaling, 1.05 x 1.25 = 1.3125 while 1.00 x 1.30 = 1.30

 

[Joe NYC]

Let's assume Arrow Lake (20A) has an 18% IPC gain. If there is a performance uplift of 10% from the silicon in addition to the 18% IPC gain. We would be looking at a 28% clock for clock gain over Raptor Lake. Even if the performance uplift was 5%, that's still over 20% performance gains over Raptor Lake. I get the 18% IPC gain from what was published for Alder Lake.

What is this 10% advantage from silicon?

I know of advantages from IPC, clock speed - for 1T
Possibly: IPC, clock speed, power efficiency - for nT

 

[Hans Gruber]

se in power consumption that people are not recognizing simply from the 20A process.

What is this 10% advantage from silicon?

I know of advantages from IPC, clock speed - for 1T
Possibly: IPC, clock speed, power efficiency - for nT

The figurative uplift in performance by switching to a new node. Eg. When AMD switched from GloFlo to TSMC 7nm. That was a huge performance uplift because TSMC silicon was far superior to GloFlo.

In theory, if Intel made Arrow Lake on 10nm and Arrow Lake on 20A. The uplift in performance of the same CPU but on different silicon. On some nodes, there is no performance uplift going from one node to another. TSMC N3 has no performance uplift but the efficiency gains are significant.

 

[Henry swagger]

Well based on info if Arrow Lake new leaks turn out to be as good as suggested and Lion Cove has much better IPC gain than expected and power consumption is reduced.

In that case I suppose Intel could beat AMD handily, though certainly not Conroe level moment.

I mean Zen 5 IPC uplift and more importantly real world performance appears underwhelming (with no clock speed bump_ and Raptor Cove already has like a 7% IPC advantage over Zen 4. If Lion Cove can achieve 20% IPC uplift over Raptor Cove and clocks can be similar, Intel could have a decent sized advantage and maybe closer to equal power consumption or only a little more? Maybe a 15% IPC advantage over Zen 5 and at similar clocks a 15% edge in single thread?

Though in gaming AMD has the X3D and as games love cache and that is games IPC, maybe AMD ties there but Intel maintains advantage by being equal in gaming to X3D and superior in other single thread things and better latency overall and better all around chip.

The above could you see happening? Certainly not the Conroe knockout moment as Conroe had even bigger IPC lead, faster clocks and much lower power consumption something of which all would not happen in above scenario.

Though could Intel deliver a single thread IPC knockout with Lion Cove over Zen 5 kind of like Golden Cove had 15% IPC over Zen 3? Difference being no or much less clock speed advantage but instead of much higher power draw as with Golden Cove to Zen 3, Lion Cove has similar power draw to Zen 5 or only marginally higher with 15% all around better IPC?

Could you see Arrow Lake being that good to have that advantage?

They will.. intel always will have the single thread crown on x86.. on apple has beaten intel with single core with the m4

 

[Henry swagger]

The difference is much smaller than that. RPC is 2-3% faster than GLC in SPEC.
Let's use benchmarks that actually matter.

View attachment 101030

edit: It's bloody stupid to use Cinebench as a proxy for general purpose performance as it's basically tests CPU performance at one particular renderer that isn't even ran on CPUs half the time.

Specint is great. But we all love pressing the cinebench button lol 😁

 

[Joe NYC]

The figurative uplift in performance by switching to a new node. Eg. When AMD switched from GloFlo to TSMC 7nm. That was a huge performance uplift because TSMC silicon was far superior to GloFlo.

In theory, if Intel made Arrow Lake on 10nm and Arrow Lake on 20A. The uplift in performance of the same CPU but on different silicon. On some nodes, there is no performance uplift going from one node to another. TSMC N3 has no performance uplift but the efficiency gains are significant.

This thing, you are thinking - it does not exist.

Better node can allow more transistors, better design - which translates to IPC
Better node can clock higher - which is just that, clock speed

That's all there is to Single Thread performance.

Multi Thread performance also involves power efficiency and power limits, which can affect at what clock speed the CPU can run at.

 

[Hitman928]

So, in the QC thread, people are saying that MTL suffers from a lack of responsiveness/lag in everyday usage (it stems from 1 reddit user sharing his experience with a new X-Elite laptop). I find it strange that I have not seen this issue mentioned at all here previously and just seemingly became a talking point with the QC laptop release. Are there any prior reports, reviews, or experiences shared about this?

 

[AMDK11]

Let's assume Arrow Lake (20A) has an 18% IPC gain. If there is a performance uplift of 10% from the silicon in addition to the 18% IPC gain. We would be looking at a 28% clock for clock gain over Raptor Lake.

Where have you achieved 10% performance(CPU) of the technological process?

Core performance is IPC + clock speed, and the process itself has nothing directly to do with it.

The technological process is intended to enable the packing of more transistors that can be used to expand the (IPC) architecture, as well as to enable a given clock frequency to be achieved at a given voltage, which affects performance and energy consumption.

Downstream technology alone, without changing the architecture or increasing clock speeds, will result in zero performance gains.

So I'm asking where did you get this 10% increase in efficiency from the technological process?

 

[coercitiv]

You are missing one key point. Since Zen 5 will not be on 3nm. Arrow Lake may be as efficient if not more than Zen 5. That may come as a complete shock to forum members here.

Did you check the power delta between N3B and N4 variant used in Zen 5? Care to share it with us?

 

[mikk]

Intel Press Event Q&A Session Lunar Lake

I haven't watched it yet, maybe they say something interesting.

 

[Hulk]

The difference is much smaller than that. RPC is 2-3% faster than GLC in SPEC.
Let's use benchmarks that actually matter.

View attachment 101030

edit: It's bloody stupid to use Cinebench as a proxy for general purpose performance as it's basically tests CPU performance at one particular renderer that isn't even ran on CPUs half the time.

The reason I often quote/post CB R23 numbers and predictions is because I have good data on how cores perform and a spreadsheet set up to make predictions. Also most people intuitively know if I write 40,000 CB R23 MT exactly how much compute that is and how it generally scales to other apps.

All of that "3345_ndks_r" stuff is kind of hard to work with when extrapolating as you have to have A LOT of data for a lot of cores and then do a lot of math work.

And I'm kind of stupid I can admit.

 

[H433x0n]

The reason I often quote/post CB R23 numbers and predictions is because I have good data on how cores perform and a spreadsheet set up to make predictions. Also most people intuitively know if I write 40,000 CB R23 MT exactly how much compute that is and how it generally scales to other apps.

All of that "3345_ndks_r" stuff is kind of hard to work with when extrapolating as you have to have A LOT of data for a lot of cores and then do a lot of math work.

And I'm kind of stupid I can admit.

Speaking of Cinebench, apparently HUB got access to a Zen 5 gaming PC before the keynote and the Cinebench score was roughly the same as Zen 4. They ended up pulling the demo and said it was pre production silicon so maybe it’s not representative. It was talked about in their podcast released today if you’re curious.

 

[ondma]

You are missing one key point. Since Zen 5 will not be on 3nm. Arrow Lake may be as efficient if not more than Zen 5. That may come as a complete shock to forum members here. The uplift from going from 10nm to 20A (5nm) may bring a significant uplift in performance beyond IPC gains. The omission of hyperthreading is offset by the enhanced e core assortment. Historically, Intel has never struggled to get impressive IPC gains when needed.

Intel said it would not be until 18A that they would have a silicon advantage over TSMC. This was many months ago and the assumption was that Zen 5 would be on 3nm. Intel has said 18A would be 10% more efficient than 20A. For that reason alone, it's good that AMD is releasing Zen 5 in July.

Arrow Lake should be compared to the Alder Lake release. A new process package and new silicon at the time 10nm. People here act as if Arrow Lake is a revision of Raptor Lake. A lot of people deny that Alder Lake was really good architecture with bad silicon compared to TSMC. Later this year they will have much better silicon and it seems like deer in the headlights for some. That's why some have said it may be another Conroe moment. The fact that 18A is the next step fairly quickly (late 2025). Intel was on 14nm for more than 6 years. Now they are planning two significant node shrinks in a year.

That's why I said in previous posts that AMD would have to have a Zen 5+ which would have to be on N3E (3nm) or similar silicon. It's not only about a performance uplift but an efficiency uplift that will make AMD relevant with 18A around the corner.

Let's assume Arrow Lake (20A) has an 18% IPC gain. If there is a performance uplift of 10% from the silicon in addition to the 18% IPC gain. We would be looking at a 28% clock for clock gain over Raptor Lake. Even if the performance uplift was 5%, that's still over 20% performance gains over Raptor Lake. I get the 18% IPC gain from what was published for Alder Lake.

If AMD goes cheap on Zen 5 silicon and goes with N4. It's highly likely that Arrow Lake may be more efficient than Zen 5. Nobody on this forum sees that coming but me. I know people are hoping Zen 5 shows up on N4X. N4P is one step down from N4X. It will be interesting to see how Turin (3nm) fares against the Intel 20A server chips in power and efficiency.

Efficiency is more than just process though. Intel's big cores seem powerful performance wise, but inefficient. I doubt a modestly more efficient process node will be enough to overcome AMD's efficiency in core design.

 

[AMDK11]

"Intel also switched from using proprietary design tools to industry-standard tools optimized for its use. Intel’s old architectures were designed with “Fubs” (functional blocks) of tens of thousands of cells consisting of manually drawn circuits, but it has now moved to using big, synthesized partitions of hundreds of thousands to millions of cells. The removal of the artificial boundaries improves design time, increases utilization, and reduces area.

This also allowed for the addition of more configuration knobs into the design to spin off customized SoC-specific designs faster, with the lead architect saying this allows for more customization between the cores used for Lunar Lake and Arrow Lake. This design methodology also makes 99% of the design transferable to other process nodes, a key advance that prevents the stumbles we’ve seen in the past where intel’s new architectures were delayed by massive process node delays (as with 10nm, for instance)."

It appears that Jim Keller contributed to the LionCove project.

EDIT:
"Intel says it widened the prediction block by 8X over the previous architecture while maintaining accuracy. Intel also tripled the request bandwidth from the instruction cache to the L2 and doubled the instruction fetch bandwidth from 64 to 128 bytes per second. Additionally, decode bandwidth was bumped up from 6 to 8 instructions per cycle while the micro-op cache was increased along with its read bandwidth. The micro-op queue was also increased from 144 entries to 192 entries."

EDIT:
It appears that LionCove is a completely redesigned core and designed from the ground up with a new approach.

 

[Hulk]

Speaking of Cinebench, apparently HUB got access to a Zen 5 gaming PC before the keynote and the Cinebench score was roughly the same as Zen 4. They ended up pulling the demo and said it was pre production silicon so maybe it’s not representative. It was talked about in their podcast released today if you’re curious.

Thanks but I based my calcs on the following from AMD. I have much more faith in this AMD released chart and I think AMD must as well to have released it. Even Intel didn't show how specific apps do with LNL IPC-wise.

 

[H433x0n]

Efficiency is more than just process though. Intel's big cores seem powerful performance wise, but inefficient. I doubt a modestly more efficient process node will be enough to overcome AMD's efficiency in core design.

Lion Cove is a departure from previous cores to address this. They backed off on widening the ROB by their typical 50%, they split the scheduler and introduced a new level of cache to increase capacity by 50% while only adding a single cycle of latency. I think this may be the first P core intel has designed that has had efficiency as a top priority.

 

[AMDK11]

Thanks but I based my calcs on the following from AMD. I have much more faith in this AMD released chart and I think AMD must as well to have released it. Even Intel didn't show how specific apps do with LNL IPC-wise.

View attachment 101057

The fact that Intel does not provide details on the IPC growth chart to which test a given bar refers to is nothing new. Intel has been doing this since SunnyCove.

Although tests later confirm this, the average is similar to what Intel reports.

 

[Hulk]

The fact that Intel does not provide details on the IPC growth chart to which test a given bar refers to is nothing new. Intel has been doing this since SunnyCove.

Although tests later confirm this, the average is similar to what Intel reports.

I didn't write they usually do this. I was simply stating the comparison to illustrate my contention that AMD must be quite confident of their IPC increase by releasing such specific data.

 

[Hulk]

Lion Cove is a departure from previous cores to address this. They backed off on widening the ROB by their typical 50%, they split the scheduler and introduced a new level of cache to increase capacity by 50% while only adding a single cycle of latency. I think this may be the first P core intel has designed that has had efficiency as a top priority.

If I remember correctly the L0 (used to be called L1) actually has 1 cycle reduced latency, from 5 cycles to 4. New L1 (actually 1.5) has 9 cycle latency and is there according to Intel to avoid going to L2 for many more situations than with Raptor Cove.

 

[poke01]

Thanks but I based my calcs on the following from AMD. I have much more faith in this AMD released chart and I think AMD must as well to have released it. Even Intel didn't show how specific apps do with LNL IPC-wise.

View attachment 101057

AMD Zen 5 CPUs/SoCs launch next month, so it’s set in stone. Intel performance metrics may increase or decrease so they wait till close to release.