Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[lightisgood]

I've heard this alleged, with no supporting data that "N3A" ever existed. Also likening any stage of N3's development to Intel's 10nm is bizarre to say the least.

I heard it form a technical writer.
N3A may have been internal nickname.
So, you can freely reject to use a word "N3A".

Anyway, TSMC made change in origin N3 node for fixing thier process bugs and postponed N3 for a whole year.

Until someone steps up with new real information, current information indicates that TSMC 3 nm issues were nowhere near what Intel went through with 10 nm.

Intel failed at 10nm, meanwhile TSMC suceeded at N7.
TSMC failed at N3, Samsung failed at 3GAE, either.
This is all what happened has then.

 

[dullard]

Problem is that ARL is late to the party. What reason will their to buy it if AMD has a comparable or better performing chip out 6 months earlier?

Please correct me if I am wrong, but Zen 5 is a July 31st release and Arrow Lake is an October release (probably announced at Intel Innovation Sept 24). That is under 3 months, not 6. If the products are comparable, then anyone buying holiday desktop computers or any desktop in H1 2025 would have a good reason to consider either company. If Zen 5 is better performing, then it comes down to availability and pricing.

 

[Saylick]

C&C has an updated Skymont article. Enjoy!

Intel Details Skymont

Previously Intel’s Skymont slides were published in low resolution, and I wrote a short article on them. Now, the presentation is public with higher resolution slides and presenter audio. Bec…

chipsandcheese.com

 

[Markfw]

C&C has an updated Skymont article. Enjoy!

Intel Details Skymont

Previously Intel’s Skymont slides were published in low resolution, and I wrote a short article on them. Now, the presentation is public with higher resolution slides and presenter audio. Bec…

chipsandcheese.com

Like reading greek for me. Question, any benchmarks ? what CPU are is this targeting ? Or is this not out yet ?

 

[Ghostsonplanets]

Like reading greek for me. Question, any benchmarks ? what CPU are is this targeting ? Or is this not out yet ?

This is a microarchitecture deep dive of the Skymont cores based on the currently released information from Intel. As you're probably aware, no product using Skymont cores has been released yet. Nor does Chips and Cheese tackle internet rumors. So questions about performance, microbenchmarking and products will need to wait until Intel and OEMs deliver products to the media.

 

[Schmide]

C&C has an updated Skymont article. Enjoy!

Intel Details Skymont

Previously Intel’s Skymont slides were published in low resolution, and I wrote a short article on them. Now, the presentation is public with higher resolution slides and presenter audio. Bec…

chipsandcheese.com

Nice highbrow veiled programmer subnormal not normal fast math O2 shade.

 

[ondma]

Please correct me if I am wrong, but Zen 5 is a July 31st release and Arrow Lake is an October release (probably announced at Intel Innovation Sept 24). That is under 3 months, not 6. If the products are comparable, then anyone buying holiday desktop computers or any desktop in H1 2025 would have a good reason to consider either company. If Zen 5 is better performing, then it comes down to availability and pricing.

I heard sometime in July for Zen 5, not necessarily as late as the 31st. As for Intel, ARL may be formally announced in October, but the latest rumors I have heard are saying it may be early 2025 for significant availability. Considering the poor availability after the Mountain Lake release, the hype given to Lunar Lake, and the general lack of emphasis on ARL, I dont find that hard to believe at all. Hell, a major laptop manufacturer whose name slips my mind right now is expressing concern that Lunar Lake will not have good availability for the holiday season. I am confused too. I thought ARL was supposed to be the next big thing, while Lunar Lake was a niche product coming after ARL. Now it seems all the emphasis has shifted to LL, not a good sign for ARL, IMO.

 

[DrMrLordX]

Anyway, TSMC made change in origin N3 node for fixing thier process bugs and postponed N3 for a whole year.

10nm was delayed by at least two years, and that's not counting the additional delays that Intel suffered even launching the aborted 10nm that went into Cannonlake. In reality the delay was more like 3-4 years before Intel even managed IceLake! There's simply no comparison.

TSMC failed at N3, Samsung failed at 3GAE, either.

3GAE never even made it to market (3GAP did though). N3 is still chugging along and will be a successful series of nodes even if you choose to deride it as a failure.

 

[dttprofessor]

intel4 - - - - - n5
intel3 - - - - - n4
intel20A- - - n3

 

[FlameTail]

Meteor Lake = RTX 2050
Lunar Lake = RTX 3050
Panther Lake = RTX 4050?

 

[poke01]

skymont has 26 execution ports more than M4-P core and X925. This is no longer a "e-core" but a "'middle" core.

 

[FlameTail]

skymont has 26 execution ports more than M4-P core and X925. This is no longer a "e-core" but a "'middle" core.

What's the definition of Middle core and E-core?

Here's the way I would classify cores:

(1) In terms of size
• HUGE (M4-P, Zen5, Lion Cove, Oryon, Cortex X925)
• BIG (Cortex A725¹, Skymont, Zen5C)
• MEDIUM (M4-E, Cortex A725²)
• LITTLE (Cortex A520)

(2) In terms of functionality
• P-core (M4-P, Zen5, Lion Cove, Oryon, Cortex X925, Cortex A725¹)
• E-core (M4-E, Zen5C, Skymont, Cortex A725², Cortex A520)

____

1 = Cortex A725 configured with high L1/L2 cache, SIMD units and frequency

2 = Cortex A725 cconfigured with low L1/L2 cache, SIMD units and frequency

 

[coercitiv]

This is no longer a "e-core" but a "'middle" core.

I think it's fair enough if you think of Skymont as M size, but E-core does no stand for S.

 

[TwistedAndy]

From an architectural standpoint, Skymont was built as a P-core and is not so different from Apple's P-cores or ARM Cortex-X2.

It can decode 9 instructions per cycle using three non-blocking decoding clusters. If there's a complex instruction requiring microcode reading, the other decoding clusters are not blocked. Intel calls it "nanocode," and on paper, it looks nice.

Apple P-cores can decode from 8 (M1) to 10 (M4) instructions per cycle.

The backend was built to handle 8 micro-ops per cycle. It's the same amount as P-cores in Apple M1 and M2.

Also, Intel decided to increase the retirement capability to 16 micro-ops per cycle in Skymont. It allowed Intel to use various buffers, queues, and register files more efficiently and avoid increasing their size too much. For comparison, the P-cores in Apple M4 can retire 10 micro-ops per cycle.

Another interesting part is the number of execution ports. Skymont has 26 of them, including 8 ALU ports, 4 128b FP ports, 3 load/4 store AGU, 3 load, and 2 store ports.

For comparison, the P-core of Apple M4 allegedly has 8 ALU, 4 FP ports, 1 port for FMA, 3 load/2 store AGU, 3 load, and 2 store ports.

Yes, we can't directly compare architectures just by the width of the decoder, execution width, buffer sizes, and the number of ports, but it can give us a rough picture of the capabilities.

If all other parts of the Skymont were balanced well, we could get ISO performance similar to the P-cores in Apple M2.

 

[TwistedAndy]

Funny enough, but Intel has used some ideas from Skymont in Lion Cove. Now, it also has a much wider retirement throughput (12 micro-ops per cycle) and separate schedulers for INT, FP, memory, etc.. Probably, in the next generations, they will split the decoder into a few clusters as well and implement faster L1 to L1 transfers.

 

[DavidC1]

If all other parts of the Skymont were balanced well, we could get ISO performance similar to the P-cores in Apple M2.

High level changes needed to get to M2 levels:
-Pipeline stages from 14 to 9(10 to 20% improvement)
-Faster and lower latency memory subsystem(includes caches)

Funny enough, but Intel has used some ideas from Skymont in Lion Cove. Now, it also has a much wider retirement throughput (12 micro-ops per cycle) and separate schedulers for INT, FP, memory, etc.. Probably, in the next generations, they will split the decoder into a few clusters as well and implement faster L1 to L1 transfers.

Maybe, but the P core team's execution sucks. Most likely the next E core will match perf/clock and the P core's only advantage will be clocks, while maintaining the 2-3x area difference.

I'm saying, whatever the next P core is after Lion Cove, Arctic Wolf will likely match it.

The P core's last innovation came with Sandy Bridge in 2011(uop cache, PRFs and other details). Rest were just expansions. The team will need a total overhaul and likely abandon the current design altogether.

 

[Ghostsonplanets]

Meteor Lake = RTX 2050
Lunar Lake = RTX 3050
Panther Lake = RTX 4050?

MTL doesn't come even close to RTX 2050 in performance. It's between a GTX 1050 to a 1650 Mobile (Very game dependent).

Panther Lake will have 50% higher resources, based on Celestial uArch and will be clocked at <=3GHz. So I expect another 2x jump and performance around GTX 1660/RTX 2060 Mobile.

 

[lightisgood]

10nm was delayed by at least two years, and that's not counting the additional delays that Intel suffered even launching the aborted 10nm that went into Cannonlake.

It seems you are based on old info.
Intel's 10nm formerly was targeted for 2016-2017, however, transferred to 2017-18 by Krzanich afterward.
This is well known as Cannon Lake, hyperscaling.
That is to say, old 10nm is not the same as Krzanich's 10nm.

In reality the delay was more like 3-4 years before Intel even managed IceLake

3-4 year? You are perfectly wrong.

3GAE never even made it to market (3GAP did though).

So, Samsung failed at 3nm after that their 1st gen 3nm was renamed as 3GAE.

 

[FlameTail]

MTL doesn't come even close to RTX 2050 in performance. It's between a GTX 1050 to a 1650 Mobile (Very game dependent).

Panther Lake will have 50% higher resources, based on Celestial uArch and will be clocked at <=3GHz. So I expect another 2x jump and performance around GTX 1660/RTX 2060 Mobile.

MTL is around 780M level, Lunar Lake is 50% faster than MTL, so LNL should be RTX 3050 level.

Of course, this is a synthetic benchmark.

 

[HoveringStyle]

In that graph the 3050 mobile is 70-90% faster than the 780m and neither configuration shown is at full power (80W TGP). LNL is not up there yet.

 

[TwistedAndy]

High level changes needed to get to M2 levels:
-Pipeline stages from 14 to 9(10 to 20% improvement)
-Faster and lower latency memory subsystem(includes caches)

I'm not sure where those numbers for pipeline stages are coming from. I have huge doubts about the Apple M2's 9-cycle latency.

As for the memory subsystem latency, it's pretty similar for Apple, Intel, AMD, and others. L1 cache usually has 4-5 cycle latency, L2 - 16-20 cycles.

In general, there's no simple answer on how to achieve a better performance. The number of pipeline stages does not matter that much. Yes, I remember those debates around Pentium 3, Netburst, etc., but now the CPUs are much more complex.

In most cases, the performance is limited to the branch predictor accuracy, OoO stuff, and a dozen other details like the execution width, load/store optimizations, etc.

For example, Intel has to add additional address-generation units (AGU) to Skymont to optimize load and store operations. There's no other sense in having four AGUs for store operations with only two store ports.

Another good example is the non-blocking decoders. For example, if the P-core in Apple M3 gets a complex instruction requiring microcode usage, it will block all 9 pipelines of the decoder. In the case of Intel, it blocks only one cluster (3 ports of 9).

In Skymont, Intel has introduced simpler L1-to-L1 data transfers without involving a fabric.

So, from my perspective, the pace of innovation in Intel's small cores is huge. They are much more interesting than P-cores. P-cores will probably become great again with rentable units, but we'll see.

As for Apple, they are pretty boring. All we see between M1 -> M4 is the widening of the existing structures without significant changes. That's not easy by any means, but it leads nowhere.

The P core's last innovation came with Sandy Bridge in 2011(uop cache, PRFs and other details). Rest were just expansions. The team will need a total overhaul and likely abandon the current design altogether.

Yep. There were some noticeable changes in Tiger Lake and Alder Lake, but they were not as dramatic as we have now in Skymont

 

[FlameTail]

@TwistedAndy CPU Microarchitecture Cheat Sheet:

Microarchitecture Cheat Sheet - Google Drive

docs.google.com

 

[poke01]

As for Apple, they are pretty boring. All we see between M1 -> M4 is the widening of the existing structures without significant changes. That's not easy by any means, but it leads nowhere.

Apple is boring because their cores are already good. To the point where Apple’s P core is more efficient and more powerful clock per clock than Skymont and LionCove.

The fact that Intel had so many new designs shows how erratic their design teams are.

Skymont is great because Crestmont sucked and it can no longer be considered an Atom core. We have yet to see how Lunar Lake performs in benchmarks and applications.

 

[Henry swagger]

Funny enough, but Intel has used some ideas from Skymont in Lion Cove. Now, it also has a much wider retirement throughput (12 micro-ops per cycle) and separate schedulers for INT, FP, memory, etc.. Probably, in the next generations, they will split the decoder into a few clusters as well and implement faster L1 to L1 transfers.

P core team need to take more ideas from Stevens's e core team.. to make the p core even more area efficient like skymont

 

[Henry swagger]

Apple is boring because their cores are already good. To the point where Apple’s P core is more efficient and more powerful clock per clock than Skymont and LionCove.

The fact that Intel had so many new designs shows how erratic their design teams are.

Skymont is great because Crestmont sucked and it can no longer be considered an Atom core. We have yet to see how Lunar Lake performs in benchmarks and applications.

Crestmont is better than bergamo. So you are wrong lol