Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[naukkis]

While I generally agree with your take on flagship vs. flagship MT performance, when it comes to i7 and especially the the i5, Intel will have the better offering. The only problem is RPL already has the better i5 over Zen 4 and that does not stop AMD from selling the R5 in particular. The halo effect from the flagships gaming CPU and the somewhat bad rep of the E cores (as in not great for games) make people chose the 6P product from AMD even when Intel has a better all-rounder in the form of 13500 for example.


According to Intel the HT performance gains is 1.3x, that's pretty close to the 0.75 factor used by @ondma in his napkin math.

Spoiler

View attachment 101751

See 30% uplift for 120% power. At other slide they tell that by dropping HT they could increase power efficiency 15%. So it's a wash - there's no benefit from HT on current power limited cpus. Specially hybrid cpu's will gain performance by giving more power to more efficient E-cores in MT workloads. And that's just what Intel did show in those slides you are referring.

 

[coercitiv]

At other slide they tell that by dropping HT they could increase power efficiency 15%.

Conveniently forgetting their third slide showing the HT enabled core having 5% better power efficiency than even the optimized core. Intel made the slides to explain why removing HT was a good idea in a product aimed at lightly threaded workloads and low energy consumption. If they removed HT from ARL then I hope they used the optimized LNC core layout, and not just disable SMT at firmware level, otherwise this will truly be a loss-loss scenario. (at least according to your PoV)

Meanwhile, as more voices pile in to explain why ARL has the winning cards on all fronts - better P core optimization by removing SMT, better E core thanks to the excellent Skymont results, more cores in general and better node thanks to the denser and slightly more power efficient N3B - it would be quite awkward if desktop Zen 5 manages to stay close or even match it in MT performance. With ARL holding all the aces, it shouldn't even get close.

 

[SiliconFly]

Conveniently forgetting their third slide showing the HT enabled core having 5% better power efficiency than even the optimized core. Intel made the slides to explain why removing HT was a good idea in a product aimed at lightly threaded workloads and low energy consumption. If they removed HT from ARL then I hope they used the optimized LNC core layout, and not just disable SMT at firmware level, otherwise this will truly be a loss-loss scenario. (at least according to your PoV)

Meanwhile, as more voices pile in to explain why ARL has the winning cards on all fronts - better P core optimization by removing SMT, better E core thanks to the excellent Skymont results, more cores in general and better node thanks to the denser and slightly more power efficient N3B - it would be quite awkward if desktop Zen 5 manages to stay close or even match it in MT performance.

Just saw a Zen5 Strix APU GB6 ST leak in X. And it's close to expectations. This year the competition is gonna be tough on both fronts (ST & MT). Exciting times ahead...

With ARL holding all the aces, it shouldn't even get close.

Too soon to be so sure! Zen is also known for coming up with surprises.

 

[naukkis]

Conveniently forgetting their third slide showing the HT enabled core having 5% better power efficiency than even the optimized core.

Take a closer look. Optimized 1t-core have that 5% better power-efficiency even against total throughput of 2-threads of HT-core. Only thing SMT core does better is performance per area - and that's forgivable for better performance.

Math could be difficult - but 15% perf increase at isopower is massive. It's more than 30% increase at 120% power level if power is limited. And it is, those stupid unlimited power levels Intel did with previous generations backfired and we will not see them in the future - and in hindsight should not have seen at all.

 

[whoshere]

Intel continues to leak their new unreleased CPUs via their testing systems:



Arrow Lake might have 24 cores. No HT in sight.

 

[coercitiv]

I see a LNL lineup leak on Videocardz:



If accurate, this confirms the ~50% delta in performance between the two core types at their max clocks.

 

[lightisgood]

I see a LNL lineup leak on Videocardz:

View attachment 101854

If accurate, this confirms the ~50% delta in performance between the two core types at their max clocks.

CU9 288V has slightly +0.1GHz clock boost, too (c.f. CU9 185H).
It looks like that N3B is almost same Intel 4 on peak FinFET performance.
I think there are 5GHz barriers.

Now I'm excited about Intel 3's peak FinFET performance.

 

[Abwx]

Math could be difficult - but 15% perf increase at isopower is massive. It's more than 30% increase at 120% power level if power is limited. And it is, those stupid unlimited power levels Intel did with previous generations backfired and we will not see them in the future - and in hindsight should not have seen at all.

Why should a core with SMT be compared to a SMT less core at different throughputs.?.
This obviously skew the results since that s not an apple/apple comparison, what matter is what power is to be used at a given and same throughput.

At 30% better throughput with SMT you can downclock by 1.30x and hence get the same throughput at about 1.2 x 0.56 = 0.67x the power, wich is 50% better perf/watt at isothroughput.

I also read that you said that the power saved by removing SMT can be transfered to the e cores, but this amount to clock them higher, wich will increase even more the inefficency of the SMT less non solution.

 

[Geddagod]

Meanwhile, as more voices pile in to explain why ARL has the winning cards on all fronts - better P core optimization by removing SMT, better E core thanks to the excellent Skymont results, more cores in general and better node thanks to the denser and slightly more power efficient N3B - it would be quite awkward if desktop Zen 5 manages to stay close or even match it in MT performance. With ARL holding all the aces, it shouldn't even get close.

Reminds me of a certain P core on Intel 7 ultra outright beating another certain P core on TSMC N5. Wasn't that awkward then....

Take a closer look. Optimized 1t-core have that 5% better power-effciency even against total throughput of 2-threads of HT-core. Only thing SMT core does better is performance per area - and that's forgivable for better performance.

I'm pretty sure Intel has stated that SMT also gives a core better perf/watt.

CU9 288V has slightly +0.1GHz clock boost, too (c.f. CU9 185H).
It looks like that N3B is almost same Intel 4 on peak FinFET performance.
I think there are 5GHz barriers.

Now I'm excited about Intel 3's peak FinFET performance.

Doubt it. Just saying, 15-30 watt Zen 4 mobile CPUs also only clocked up to 5.1GHz, despite, as we know, Zen 4 is able to hit what, 5.7, 5.8GHz?

 

[naukkis]

Why should a core with SMT be compared to a SMT less core at different throughputs.?.
This obviously skew the results since that s not an apple/apple comparison, what matter is what power is to be used at a given and same throughput.

At 30% better throughput with SMT you can downclock by 1.30x and hence get the same throughput at about 1.2 x 0.56 = 0.67x the power, wich is 50% better perf/watt at isothroughput.

I also read that you said that the power saved by removing SMT can be transfered to the e cores, but this amount to clock them higher, wich will increase even more the inefficency of the SMT less non solution.

Intel p-core team did in their slides. Their optimized SMTless core beat SMT-version throughput even when counting SMT-version two threads together. Your calculations aren't right because you are comparing against cpu with HT running one thread instead of SMT less optimized core like Intel did.

And if e-cores would need to clock above their efficiency point Intel could increase those count - ruining big cores with SMT isn't bringing any benefits to hybrid cpus. That's too is well mentioned in Intel P-core team presentation.

 

[Abwx]

Intel did in their slides. Their optimized SMTless core beat SMT-version throughput even when counting SMT-version two threads together. Your calculations aren't right because you are comparing against cpu with HT running one thread not to SMT less optimized core like Intel did.

My calculations are right, it s just that Intel is aware that not everybody can do efficency evaluations.

And actually what they are doing is to increase the core count as a mean to increase efficency by using 2 cores instead of one, that s the only case where their discourse hold.

Rather than using a core that output 130 with SMT at a frequency of 100 and power of say 13W they use 2 comparable cores that are clocked at 65 to get a 130 throghput, in this case their 2 cores will consume 8W for the same 130 throughput, wich is 62.5% better perf/Watt.

 

[naukkis]

My calculations are right, it s just that Intel is aware that not everybody can do efficency evaluations.

And actually what they are doing is to increase the core count as a mean to increase efficency by using 2 cores instead of one, that s the only case where their discourse hold.

Rather than using a core that output 130 with SMT at a frequency of 100 and power of say 13W they use 2 comparable cores that are clocked at 65 to get a 130 throghput, in this case their 2 cores will consume 8W for the same 130 throughput, wich is 62.5% better perf/Watt.

Their SMT-less core has 115 performance at 100% power. Their possible HT version would have 130 performance at 120% power. So HT does not bring any throughput increase at isopower. And that's not even apples to apples comparison, pretty much nobody needs pure throughput at desktop or mobile - what they need is MT-performance and biggest factor to have it is to have best possible ST-performance to scale other threads too.

 

[Abwx]

Their SMT-less core has 115 performance at 100% power.

You mean that the SMTed core has 115% of the power at same perf.?.
Because 15% better perf at same power is not possible, this would amount to comparison with a SMT core using roughly 35% more power at same perf.

In wich case those 35% can be used to clock a SMT less core 15% higher at same power.

Their possible HT version would have 130 performance at 120% power. So HT does not bring any throughput increase at isopower. And that's not even apples to apples comparison, pretty much nobody needs pure throughput at desktop or mobile - what they need is MT-performance and biggest factor to have it is to have best possible ST-performance to scale other threads too.

If its perfs are 130 at 120% of the power then perf will be 120 at 100% of the power.

Eventually they removed SMT for other reasons that stated, perhaps that it doesnt bode well with a uarch using hybrid cores and that it doesnt cost that much to replace a SMT thread by a relatively small core.

 

[naukkis]

You mean that the SMTed core has 115% of the power at same perf.?.
Because 15% better perf at same power is not possible, this would amount to comparison with a SMT core using roughly 35% more power at same perf.

In wich case those 35% can be used to clock a SMT less core 15% higher at same power.

Just like Intel demonstrated, they have 115% single-thread performance at same power with their single-thread optimzed core as SMT-core running one thread. At that same power level SMT-cores both combined threads execute 130% instructions compared to that same core with single thread - performance from two combined threads aren't directly comparable to single threads as splitting work to two threads will decrease efficiency. They even know that and put it that way that it's technically correct - newer compare multiple threads performance to single thread directly.

 

[naukkis]

And I have to wonder why there's so much love towards SMT in this forum. Most desktop users won't benefit at all from SMT but would from reverse SMT - rentable units of whatever - which would use unused cores/parts of them to boost single-thread performance.

 

[Nothingness]

Just like Intel demonstrated, they have 115% single-thread performance at same power with their single-thread optimzed core as SMT-core running one thread.

They didn't demonstrate anything: they made a claim with a footnote saying ""All figures based on hypothetical comparison of HT-capable P-core vs Optimized P-core".

 

[SarahKerrigan]

And I have to wonder why there's so much love towards SMT in this forum. Most desktop users won't benefit at all from SMT but would from reverse SMT - rentable units of whatever - which would use unused cores/parts of them to boost single-thread performance.

And I can't understand why you've made it your life's mission to turn an Intel marketing slide into a permanent anti-SMT crusade.

They didn't demonstrate anything: they made a claim with a footnote saying ""All figures based on hypothetical comparison of HT-capable P-core vs Optimized P-core".

This. There was no real discussion of methodology whatsoever. It has no value. It has about as much technical value as a slide saying "SarahKerrigan is the most awesomest in the whole world!"

 

[naukkis]

They didn't demonstrate anything: they made a claim with a footnote saying ""All figures based on hypothetical comparison of HT-capable P-core vs Optimized P-core".

That's how cpu's are designed - in simulations. That's Intel demonstration of different design approaches and it's effect on cpu performance and efficiency is actually by far the best we have seen in years coming from cpu manufacturers. But those same simulations and their actual comparisons to silicon implementations are demonstrated from other manufacturers too - and when simulation and silicon implementation differs from each other don't expect great performance from actual silicon.

 

[SarahKerrigan]

That's how cpu's are designed - in simulations. That's Intel demonstration of different design approaches and it's effect on cpu performance and efficiency is actually by far the best we have seen in years coming from cpu manufacturers. But those same simulations and their actual comparisons to silicon implementations are demonstrated from other manufacturers too - and when simulation and silicon implementation differs from each other don't expect great performance from actual silicon.

Other manufacturers, a lot of them, have said there are huge gains from SMT. Look at what Marvell says. They went into more detail than Intel did.

If Intel wants to provide methodology in a paper or an ISSCC presentation, I'll listen to it. A marketing slide is worthless. Years paying close attention to Intel's marketing claims, both on IPF and x86, have made me look at them critically; it is not the word of God to me.

 

[naukkis]

And I can't understand why you've made it your life's mission to turn an Intel marketing slide into a permanent anti-SMT crusade.

Actually Intel put on their slides those exact points I have made in this forum years. I actually thought that those Intel points would made my point stronger but resistance in this forum is strong

 

[SarahKerrigan]

Actually Intel put on their slides those exact points I have made in this forum years. I actually thought that those Intel points would made my point stronger but resistance in this forum is strong

And because it confirms your biases, you take it as gospel and ignore Marvell saying they get 28%-121% increase in throughput perf, depending on workload, for an area cost of 5%.

 

[naukkis]

Other manufacturers, a lot of them, have said there are huge gains from SMT. Look at what Marvell says. They went into more detail than Intel did.

If Intel wants to provide methodology in a paper or an ISSCC presentation, I'll listen to it. A marketing slide is worthless. Years paying close attention to Intel's marketing claims, both on IPF and x86, have made me look at them critically; it is not the word of God to me.

You are missing a point. Intel P-cores aim to be 1T performance king. Competition is though nowadays - 1T performance crown won't come easily. SMT isn't a free lunch anymore, core to target 1T need to drop it and only AMD seems to disagree now.

 

[naukkis]

And because it confirms your biases, you take it as gospel and ignore Marvell saying they get 28%-121% increase in throughput perf, depending on workload, for an area cost of 5%.

Those Marvell cpu's did so well - specially on 1T. Yeah SMT has it's strong points but those aren't found in todays desktop or mobile cpus.

 

[SiliconFly]

Just like Intel demonstrated, they have 115% single-thread performance at same power with their single-thread optimzed core as SMT-core running one thread. At that same power level SMT-cores both combined threads execute 130% instructions compared to that same core with single thread - performance from two combined threads aren't directly comparable to single threads as splitting work to two threads will decrease efficiency. They even know that and put it that way that it's technically correct - newer compare multiple threads performance to single thread directly.

Nicely said. 15% more ST at same power when HT is completely removed. Thats should be reason enough to remove HT completely. Let the gazillion E cores handle MT.

 

[Nothingness]

That's how cpu's are designed - in simulations.

Really? /s

That's Intel demonstration of different design approaches and it's effect on cpu performance and efficiency is actually by far the best we have seen in years coming from cpu manufacturers. But those same simulations and their actual comparisons to silicon implementations are demonstrated from other manufacturers too - and when simulation and silicon implementation differs from each other don't expect great performance from actual silicon.

They don't even talk about simulations. They talk about "hypothetical comparison". It would be an interesting exercise to read the footnotes of their previous marketing announcements of CPU. I bet they never used the word "hypothetical".

If you were working in a CPU design team, you'd be surprised by how inaccurate power projections (yes, projections, because you can't fully do power simulations, that's extraordinary expensive) can be. I'm not saying it's the case for Intel, they have a lot more experience than the teams I've worked with in that domain. But I doubt their power projection results would be as accurate as you think.

EDIT: BTW I'm not defending SMT.