Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[SiliconFly]

There is no evidence that Arrow Lake is the same tile generation as MTL. I cannot be, different Node, different Fovo gen, different everything. I think they learned a lesson from MTL and implemented some changes to compensate the shortcomings.

Yep. We still don't know for sure. But initial rumors (even before MTL release) said ARL will reuse the same tile layout and the same soc tile with the 2LPE crestmont e cores will be reused. Yet to be confirmed.

 

[SiliconFly]

... Let me put it this way. Both Intel and AMD camp are disappointed, and people are in still denial. ...

That part is so true!

 

[SiliconFly]

deleted

 

[Doug S]

What are the prospects for Nova Lake? Is it still a thing? I thought it (Nova Lake link) was supposed to be the biggest architectural change in Intel's history, and expected to bring a huge IPC gain (up to 50%)? Intel definitely needs to step up their game on the P core front.

Nobody is making a 50% IPC gain in a single generation, that's simply not possible.

It also doesn't make sense they'd use TSMC N2 when 18A is supposed to be ready before it (if not 14A!) and they keep claiming they are going to achieve process leadership. That article reads like someone's wet dream about what they want to happen, much like how people here were building up all this hype for Zen 5 to gain 40% or more IPC.

 

[poke01]

Nova lake is likely an 15%-20% IPC gain. It that’s to be expected as it’s not launching till late 2026.

 

[Magio]

It also doesn't make sense they'd use TSMC N2 when 18A is supposed to be ready before it (if not 14A!) and they keep claiming they are going to achieve process leadership

I generally agree with what you said regarding the article being make-believe and 50% IPC a pipe dream, but just regarding this: Even if/when Intel regains process leadership (potentially with 18A) and even if/when that lead is significant (potentially with 14A or 10A), they will be continuing to leverage TSMC nodes long term.

Even if they could, which is not a certainty, ramp their leading edge nodes fast enough to cover their entire (high end) product line within reasonable time frames, they couldn't do that *and* have capacity to spare for foundry contracts with major players which are a key aspect of their new strategy.

So for the foreseeable future it will continue to make sense for Intel to have certain products, including halo products in certain segments, built on TSMC nodes partially or completely.

 

[SiliconFly]

Nobody is making a 50% IPC gain in a single generation, that's simply not possible.

It also doesn't make sense they'd use TSMC N2 when 18A is supposed to be ready before it (if not 14A!) and they keep claiming they are going to achieve process leadership. That article reads like someone's wet dream about what they want to happen, much like how people here were building up all this hype for Zen 5 to gain 40% or more IPC.

If I remember right, very old rumors suggested that nova lake will offer 50% IPC uplift over GLC or something like that (not gen-over-gen). All these articles somehow manage to misinterpret one rumor and manage to spread more fake rumors based on the already unverified rumor and try to present it as facts. It's a systemic issue I'd say.

 

[SiliconFly]

I generally agree with what you said regarding the article being make-believe and 50% IPC a pipe dream, but just regarding this: Even if/when Intel regains process leadership (potentially with 18A) and even if/when that lead is significant (potentially with 14A or 10A), they will be continuing to leverage TSMC nodes long term.

Even if they could, which is not a certainty, ramp their leading edge nodes fast enough to cover their entire (high end) product line within reasonable time frames, they couldn't do that *and* have capacity to spare for foundry contracts with major players which are a key aspect of their new strategy.

So for the foreseeable future it will continue to make sense for Intel to have certain products, including halo products in certain segments, built on TSMC nodes partially or completely.

Exactly! Intel's own leading edge nodes are gonna take a year or two to ramp up to full volume (and also improve yield). Until then they won't have the capacity they need and have to rely on external foundries to fulfill their own client/server orders that are on leading edge nodes.

"As you adequately put, the problem is capacity!". -The Architect.

 

[Hulk]

I realize that Cinebench R23 ST isn't representative of a variety of software but I have this data that I believe is semi-reliable so I thought I would present this graph I created.

Intel was slowly "tick-tocking" along up until Skylake. The trouble with 10nm and a big rush to get Cypress Cove and Golden Cove out the door!

edit - Should be points/GHz, not MHz

 

[Doug S]

Exactly! Intel's own leading edge nodes are gonna take a year or two to ramp up to full volume (and also improve yield). Until then they won't have the capacity they need and have to rely on external foundries to fulfill their own client/server orders that are on leading edge nodes.

"As you adequately put, the problem is capacity!". -The Architect.

Its a really bad look if Intel's premium chips are coming out on someone else's process. They are supposedly looking at $15 billion in external foundry business by the end of the decade versus nearly $100 billion in internal volume, so it isn't as if they have a ton of external business pushing them to TSMC. They used to be able to supply their own needs - and they had a larger market share in those pre Zen days. So what happened? Do they have fewer fabs than they did 10 years ago?

I could see using TSMC for lower end/volume Celeron/Pentium/i3 type stuff, lower tier GPU chiplets, and the like but this is a rumor about some fabled new architecture that's going to let Intel from the wilderness and drive a stake in AMD's heart (or at least it would if that 50% was even close to real) Surely they could devote their best capacity to THAT, and use TSMC for all the trash that gets put into PCs costing $500 and under.

 

[SiliconFly]

Its a really bad look if Intel's premium chips are coming out on someone else's process. They are supposedly looking at $15 billion in external foundry business by the end of the decade versus nearly $100 billion in internal volume, so it isn't as if they have a ton of external business pushing them to TSMC. They used to be able to supply their own needs - and they had a larger market share in those pre Zen days. So what happened? Do they have fewer fabs than they did 10 years ago?

I could see using TSMC for lower end/volume Celeron/Pentium/i3 type stuff, lower tier GPU chiplets, and the like but this is a rumor about some fabled new architecture that's going to let Intel from the wilderness and drive a stake in AMD's heart (or at least it would if that 50% was even close to real) Surely they could devote their best capacity to THAT, and use TSMC for all the trash that gets put into PCs costing $500 and under.

To be self-sustainable, Intel requires a lot of forward-looking vision. Something they seriously lacked until a few years ago. All thanks to the bean counters. For large capacity, new (heavy) investments in foundry is required and most importantly an investment now, takes a few years to translate to real world capacity.

That is exactly what has happened now. Intel is heavily invested in High-NA. In fact they've booked an entire years supply just to block the competition and build leading-edge capacity ahead of the rest. Assuming all goes well, Intel should have leading-edge capacity after the launch of 14A (not before and not during).

Until then, they have to rely a little bit on external foundries too for their leading-edge volume products (two years at least, even three maybe).

 

[csbin]

ARL/LNL different

https://twitter.com/x/status/1807703815510171722

 

[jpiniero]

Its a really bad look if Intel's premium chips are coming out on someone else's process. They are supposedly looking at $15 billion in external foundry business by the end of the decade versus nearly $100 billion in internal volume, so it isn't as if they have a ton of external business pushing them to TSMC. They used to be able to supply their own needs - and they had a larger market share in those pre Zen days. So what happened? Do they have fewer fabs than they did 10 years ago?

Um... this has been discussed just in this thread multiple times. Intel doesn't have the money.

 

[coercitiv]

Saw this on Videocardz, a diagram for 800 series and Arrow Lake-S I/O capabilities:

The good news is we're apparently getting another bundle of PCIe lanes that can be used for a second SSD connected directly to the CPU.

 

[poke01]

integrated TB4 finally

 

[dullard]

Desktop arrow lake will have lp cores according to mild

Then he's very wrong. Unless he got some hot off the press info

MLID claims the LP-E cores are in Arrow Lake. But he didn't specify desktop, mobile, or both. https://videocardz.com/newz/intel-r...-refresh-featuring-8p32e-cores-for-2025-debut

WCCFTech claims that mobile Arrow Lake will have LP-E cores--Crestmont based, not Skymont based. https://wccftech.com/intel-arrow-la...ke-h-16-core-cpus-spotted-higher-base-clocks/ and https://wccftech.com/intel-arrow-lake-cpu-core-ultra-200-branding-raptor-lake-h-refresh-core-200h/

TechSpot (via Golden Pig) claims mobile Arrow Lake will have LP-E cores, but not desktop. https://www.techspot.com/news/102149-intel-arrow-lake-s-desktop-processors-ditch-lp.html

 

[TwistedAndy]

MLID claims the LP-E cores are in Arrow Lake. But he didn't specify desktop, mobile, or both.

It appears that both the desktop (ARL-S and ARL-S) and mobile (ARL-H) will have LP-E cores. They are not necessary for desktops but might be pretty useful for ARL-H and ARL-HX. The same can be said about two embedded TB4 controllers.

It looks like Intel is going to make ARL-HX more mobile-friendly while using the unified design with desktop ARL-S.

 

[DavidC1]

ARL/LNL different

https://twitter.com/x/status/1807703815510171722

So the IMC is in SoC Tile just like Meteorlake. 3MB L2 won't affect performance in a meaningful way.

Wonder what the performance impact is changing the layout of the cores?

 

[TwistedAndy]

Wonder what the performance impact is changing the layout of the cores?

The performance impact of moving the IMC to the SoC tile will be minimal (0-5% IPC). Here's a comparison of Raptor Lake (13500H) to Meteor Lake (125H):

 

[SiliconFly]

It appears that both the desktop (ARL-S and ARL-S) and mobile (ARL-H) will have LP-E cores. They are not necessary for desktops but might be pretty useful for ARL-H and ARL-HX. The same can be said about two embedded TB4 controllers.

It looks like Intel is going to make ARL-HX more mobile-friendly while using the unified design with desktop ARL-S.

It's already kinda established that those 2 Crestmont LPE cores in MTL SoC tile aren't powerful enough to handle the background tasks. If the same cores are gonna feature in ARL, they're still not gonna be very useful. Or am I missing something crucial?

 

[DavidC1]

2. If #2 is not the case (the sequential nature of the code isn't the main bottleneck) then could it be that the current P core architecture has maxed out from an IPC point-of-view and a completely new and different direction is required, something more along direction of Skymont?

It can't be the limit, because clearly Apple is way higher.

Based on David Huang's analysis, Zen 5 is a regression in structure size for many aspects, looking more like a careful(attempted?) balance to increase performance.

That's likely the reason for why Zen 5 didn't increase in performance so much. Smaller uop cache, reduced performance in certain instructions and the clustered decode setup akin to Tremont but a more niche implementation that doesn't work as often in ST and is tailored for more MT performance. It's probably better for perf/watt but not outright performance.

We can't say sure for Lion Cove yet, but we don't know the full details on why the gain is only 16% for such a big on paper improvement. Think of RDNA3 how on paper it looked impressive but turned out to be a situational benefit and it was done to save area with the dual issue unit. It could be the Lion Cove core just like Zen 5 and RDNA3 took steps to reduce gains in transistor count thus the performance ended up middling.

Also don't discount the possibility that the team could simply not be executing that well.

MLID claims the LP-E cores are in Arrow Lake. But he didn't specify desktop, mobile, or both. https://videocardz.com/newz/intel-r...-refresh-featuring-8p32e-cores-for-2025-debut

It's useless in Meteorlake, so it'll be worse in Arrowlake. They probably didn't bother changing the SoC Tile much from the MTL version if it indeed is found to have the LPE cores. The utopian idea that chiplets/tiles will allow changing every block with no consequence is probably just that - a dream.

Hopefully at least it's more power efficient rather than the amazing 150mW savings only possible when it's a best case scenario.

 

[dullard]

It's already kinda established that those 2 Crestmont LPE cores in MTL SoC tile aren't powerful enough to handle the background tasks. If the same cores are gonna feature in ARL, they're still not gonna be very useful. Or am I missing something crucial?

I think there were two main issues with the Meteor Lake's LP-E implementation.

1) There were 4 types of ways to run a thread. Threads ran on (1) P cores, (2) E cores, (3) LP-E cores, and (4) hyperthreading on the P cores. Scheduling this was not as good as Intel hoped. Too many options and not enough software written yet to specify which core to run on.

2) The LP-E cores were just clocked too low. The goal was to be as low of power as possible, but Intel went too low. Depending on the CPU, the LP-E cores in Meteor Lake had a base clock of 400 MHz to 1 GHz! When was the last time you ever felt 400 MHz to be sufficient? Turbo clocks were also pretty low: 2.1 GHz to 2.5 GHz and that is if there was thermal and power headroom to do turbo.

If (and this is an if that seems likely) Arrow Lake ditches hyperthreading, then the scheduling does get significantly easier to get right. And if the much smaller node lets them run faster, then I think the LP-E cores could actually perform how they were intended.

 

[DavidC1]

2) The LP-E cores were just clocked too low. The goal was to be as low of power as possible, but Intel went too low. Depending on the CPU, the LP-E cores in Meteor Lake had a base clock of 400 MHz to 1 GHz! When was the last time you ever felt 400 MHz to be sufficient? Turbo clocks were also pretty low: 2.1 GHz to 2.5 GHz and that is if there was thermal and power headroom to do turbo.

The Skymont cores on Lunarlake runs 10% faster clocks with twice the amount of cores while performing 38%/68% faster per clock for MT, and runs 70% faster in ST, meaning it gets both uarch benefit and clock increases.

Meteorlake's measurements show that the LPE cores were useless, consuming more power than the E cores at all frequency levels. The E core was more efficient than the "LP" E cores and not by a small amount.

I am not sure if they really need a third cluster and if they could just make it work with two clusters like with Lunar Lake. It would be easier to just disable a cluster completely if low power operation is needed from a scheduling point of view.

 

[TESKATLIPOKA]

No one seems to mind that LNL iGPU performance shown in two least representative 3DMark tests, TS and WLE.
At least with ARC, TS score has little to do with gaming performance. The same goes for Nomad

The Fire Strike Extreme is way more suitable for comparing Intel and AMD GPUs in real-world gaming tasks.

LNL has a new GPU architecture, so we don't know If TS score will be inflated or not or by how much compared to MTL.
On the other hand, even If It is inflated, It is not a low value.
If It was TS Graphics, It would be better, but whatever.

TS score(Highest for the given TDP from notebookcheck database):
15/15W 8840U -> 2688 (100%)
17W LNL -> 3438 (128%)
64/20W MTL 185H -> 3537 (132%)

32/27W 8840HS -> 3203 (99%)
54/28W 7840U -> 3232 (100%)
64/28W MTL 155H -> 3710 (115%)
30W LNL -> 4151 (128%)

At low TDPs It looks the most impressive. If Intel will keep improving their drivers, then It could be interesting.

edit: added PL2 for Phoenix and 8840HS.

 

[SiliconFly]

... And if the much smaller node lets them run faster...

But aren't they reusing the exact same TSMC N6 SoC tile from MTL? If thats the case, how can we expect any improvement?

... When was the last time you ever felt 400 MHz to be sufficient? ...

The good ol' days when doom and quake were rocking the scene!