Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[FlameTail]

ADL-N refresh

WDL is the successor using Darkmont cores.

Tell what the abbreviations stand for!

 

[FlameTail]

LPDDR6 is expected to be introduced this year. Rumors suggest that Snapdragon 4 Gen 4 and Apple A18 will use LPDDR6.

Most likely not.

 

[FlameTail]

This leak from a while ago suggested that PTL is LPDDR5X:

Intel Arrow Lake "Core Ultra 200" & Panther Lake "Core Ultra 300" Laptop CPUs Leak Out

Intel's next-generation Arrow Lake "Core Ultra 200" & Panther Lake "Core Ultra 300" CPUs for laptops have been spotted in multiple leaks.

wccftech.com

Furthermore, it looks like Intel is going to incorporate LPDDR5X on-package memory again with Panther Lake-U low-power SKUs for thin and light platforms. Intel has already confirmed that its Panther Lake lineup will scale up what Lunar Lake had to offer and will offer more flexible DRAM configurations so you won't be limited to just 16 GB or 32 GB LPDDR5X capacities

Is that the actual leak, or speculation from the Wccfkek author?

 

[uzzi38]

Panther Lake is a 2026 product that is not Pin-to-Pin compatible with Arrow Lake, according to the recent Clevo's leak:

View attachment 102366

I don't see any good reason to change the pin layout for Panther Lake and then change it again for the LPDDR6 support in the next platform a year later.

Intel will probably switch to LPDDR6 with Panther Lake and use the next 2027 mobile platform as a drop-in replacement. Many OEMs are used to Intel's two-year cycles (new platform -> drop-in refresh -> new platform)

Not being pin compatible doesn't tell you much, it certainly isn't enough on it's own to imply a switch to LPDDR6. It just means there's significant enough changes to warrant breaking compatibility from one generation to the next (which Intel does anyway every couple of generations).

Given the popularity of LNL, I wouldn't be surprised if PTL just looks more like LNL in terms of layout, and the switch to that layout makes it not worth it to keep it pin-to-pin compatible.

 

[TwistedAndy]

Not being pin compatible doesn't tell you much, it certainly isn't enough on it's own to imply a switch to LPDDR6. It just means there's significant enough changes to warrant breaking compatibility from one generation to the next (which Intel does anyway every couple of generations).

Given the popularity of LNL, I wouldn't be surprised if PTL just looks more like LNL in terms of layout, and the switch to that layout makes it not worth it to keep it pin-to-pin compatible.

I do not think that PTL-U will use the on-package memory. PTL-U has the U letter, not V.

The new SoC tile in PTL and ARL refresh will probably support both LPDDR5/5X and LPDDR6, as we have seen with Alder Lake and DDR4/DDR5.

Intel needs Lunar Lake for a few reasons:
1. Have a platform with the updated NPU for Copilot+ systems before PTL-U with a new SoC tile is released
2. Test and debug the new SoC tile, GPU, and a lot of other new techs before implementing it in the much more widely used refreshed ARL and PTL.

Once the PTL-U is released, Intel will no longer need Lunar Lake.

 

[Ghostsonplanets]

Tell what the abbreviations stand for!

ADL-N - Alder Lake Intel Processor and i3 N series which uses Gracemont cores only
TWL - Twin Lake Refresh of ADL-N series

WCL - Wildcat LakeSuccessor of ADL-N

I do not think that PTL-U will use the on-package memory. PTL-U has the U letter, not V.

PTL-U will have some SKUs with PoP memory. They'll be branded accordingly.

It's needs to be remembered that while these are U branded SKUs, they won't be sold at cheap prices but rather at premium mainstream. It will take a while for Intel Tiled designs to come to the usual budget mainstream devices.

 

[Kepler_L2]

The new SoC tile in PTL and ARL refresh will probably support both LPDDR5/5X and LPDDR6

Very difficult to do given the large changes in LP6.

 

[cannedlake240]

ADL-N - Alder Lake Intel Processor and i3 N series which uses Gracemont cores only
TWL - Twin Lake Refresh of ADL-N series

WCL - Wildcat LakeSuccessor of ADL-N

PTL-U will have some SKUs with PoP memory. They'll be branded accordingly.

It's needs to be remembered that while these are U branded SKUs, they won't be sold at cheap prices but rather at premium mainstream. It will take a while for Intel Tiled designs to come to the usual budget mainstream devices.

PoP memory? As on mobile socs? Guess intel wants to revive its mobile business, but they don't even have a modem department... They should reacquire it from apple

 

[Ghostsonplanets]

PoP memory? As on mobile socs? Guess intel wants to revive its mobile business, but they don't even have a modem department... They should reacquire it from apple

Meant to say on-package, sorry. Autocorrect changed it

Same as Lunar Lake basically.

 

[cannedlake240]

Curious if PTL-Ux can improve on LNL light load efficiency Because LNL supposedly still isn't quite there yet to challenge arm competition, and if PTL regresses in that aspect Intel stands to lose market and mind share to Arm and company. They must disprove the arm superiority narratives to stay relevant

Also does PTL retain the SLC from LNL? From the wafer they showed at computex, individual tiles appear too small to house the SLC and all the other ip including npu, cpu, ipu, LP island etc. It also could be on the base tile, that could be interesting. Base tile on i3 could fit a larger SLC

 

[TwistedAndy]

Very difficult to do given the large changes in LP6.

Yes, it will be challenging to implement, but Intel may find a solution.

The current engineering samples of ARL-P, PTL-U, and PTL-H are being tested with the LPDDR5X memory kits. They are marked as T3 and T4, but I'm not entirely sure what it means.

 

[DavidC1]

Curious if PTL-Ux can improve on LNL light load efficiency Because LNL supposedly still isn't quite there yet to challenge arm competition, and if PTL regresses in that aspect Intel stands to lose market and mind share to Arm and company.

It doesn't seem behind based on them saying it beats it on Teams for example.

Small regression is fine. What is allowing WoA resurgence is the massive 50%-plus difference. If it's 10-15% then it won't be a big deal at all.

Also does PTL retain the SLC from LNL? From the wafer they showed at computex, individual tiles appear too small to house the SLC and all the other ip including npu, cpu, ipu, LP island etc. It also could be on the base tile, that could be interesting. Base tile on i3 could fit a larger SLC

SLC makes little sense when it has many tiles like MTL, ARL, and PTL. Lunarlake has only two.

So far I'm not impressed with PTL. Regression back to many tiles, dedicated LP-E cores again. Complex approaches rarely ever work out.

Once the PTL-U is released, Intel will no longer need Lunar Lake.

Or, Lunarlake saps the energy out of the WoA competition that they can go back to not needing it again, with "good enough" designs such as PTL-U being sufficient.

One thing Gelsinger has to prove is that Intel isn't a reactive company anymore. They got Celeron line out only because Cyrix wanted to target low end exclusively. Pentium M was a response to Transmeta basically. Atom is ARM. It maximizes short term gains but it completely jeopardizes long term life of the entire company.

How much better of a position would they be in if they were all natural progressions?

 

[DavidC1]

So they released a single SKU in a low volume non performance sensitive embedded market just so they could claim "we're shipping", even though they knew 10nm was nowhere near ready. There was no "learning" involved in this, it was simply a scam launch. That is made evident by the fact that Cannon Lake was just this single SKU and the next 10nm part didn't arrive until sixteen months had passed!

That angle is there for sure, but that little product is enough for yield learning, when up until that point the delays were endless. There's confidence involved as well, where until release everyone was jeering against them and confidence was close to zero. It was haphazard for sure, but Icelake followed up fairly quickly.

Sixteen months is not a long time when you consider it was a dramatic improvement, and Icelake was a tock in terms of changes. They couldn't make a mere refresh work with 10nm with CNL, but just 16 months later they get 10nm working and substantial core changes in both CPU+GPU.

It also supports what they are doing with 4/3 and 20/18A. Is there anyone saying Intel 4 is a good process by any means? What is impressive even a little about Meteorlake? Or that 20A will be basically CNL all over again?

How do we get "conspiracy theories" out of what seems pretty obvious, that they are likely not ready for real good product that 20A is being featured in the Desktop market and only with 6+8? It is likely a mediocre process, plain and simple.

 

[SiliconFly]

... that 20A is being featured in the Desktop market and only with 6+8? It is likely a mediocre process, plain and simple.

Thats got to be so true. Only hiccup is, it's better than competition.

 

[Doug S]

I added a credible leak to support my claim

Let's analyze that chart closely. Intel is going to update the pinout for PTL-U and PTL-H. This platform will be released in 2026 and actual devices will appear in Q1 or Q2 2026. The following platform released in 2027 will use the same pinout as Panther Lake.

Intel did that with CFL/TGL, ADL/RPL, MTL/ARL, and will continue with PTL and the next platform. It's too expensive for OEMs to redesign a platform every year.

DDR5/LPDDR5 is currently 4-5 years old and slowly reaching its limits. In 2026 and 2027, it will be completely obsolete, especially considering the AI hype. Those "++TOPS" we see on the chart require more memory bandwidth, so LNL is using one of the fastest LPDDR5 memory.

LPDDR6 is expected to be introduced this year. Rumors suggest that Snapdragon 4 Gen 4 and Apple A18 will use LPDDR6. I do not see any reason why it will not be available in 2026.

Anyone who would give even the TINIEST bit of credence to a rumor that Apple A18 will use LPDDR6 has no ability to discern credible rumors from absolute fantasy. JEDEC has not even officially finalized and "delivered" the LPDDR6 standard yet, which means LPDDR6 isn't even sampling yet (a few pre-standard parts to show off in a display at a conference is not "sampling")

Where could Apple get LPDDR6 to make millions of iPhones containing A18 that will ship in less than three months, out of the back of a DeLorean?

 

[AMDK11]

A few thoughts on CPU-Z results (to put it very simply):

Zen 1 has a separate scheduler for FPU and a separate scheduler for ALU with dedicated execution ports (4x FPU + 4x ALU) while Skylake has a unified scheduler and 3x FP/ALU + 1x ALU. This may be the reason for Zen1's initially higher score.

No CPU-Z IPC increase for Zen4 compared to Zen3: Zen4 and Zen3 each have 4xALU and 6xFPU as well as a 4-wide decoder.

GoldenCove has a 6-wide decoder, 3x FP/ALU + 2x ALU, which gives a total of 5x ALU.

Maybe Intel's favoritism lies in the specificity of the CPU-Z test?

Intel with LionCove abandons unified scheduler and execution ports for FPU and ALU. RedwoodCove is the last core with 3xFP/ALU + 2xALU and the transition to 4xFPU + 6xALU in LionCove. I think that LionCove's behavior in many situations will be different than GoldenCove's.

 

[DavidC1]

A few thoughts on CPU-Z results (to put it very simply):

Isn't there a 14900K result with even higher ST result than the prototype Arrowlake?

 

[H433x0n]

Isn't there a 14900K result with even higher ST result than the prototype Arrowlake?

It's not a real benchmark result. Even if it were, I can't overstate how pointless this benchmark is.

 

[DavidC1]

It's not a real benchmark result. Even if it were, I can't overstate how pointless this benchmark is.

This is why SPEC is still favored.

You have Geekbench that abandoned being able to sort in GB4. In GB5 they stopped separating Int and FP results, and GB6 they added a niche instruction. Like do they understand their jobs?

This is from C&C for CPU-Z

I can’t think of anything that fits within the L1 cache and barely challenges the branch predictor. CPU-Z’s benchmark is an exception.

So basically they are saying it's Dhrystone all over again. At least Dhrystone benchmarked pure performance of the ALU. CPU-Z is measuring what again?

They gave a Yellow star for effort. LOL!

 

[Hulk]

It's not a real benchmark result. Even if it were, I can't overstate how pointless this benchmark is.

The point of a benchmark is to measure performance. It doesn't really matter what performance is measured if at the end of the day so long as the benchmark correctly orders the processors tested by overall performance, and identifies the magnitude of performance difference among them. The caveat here would be if you were looking at performance for a specific application, then of course go find scores for that application. But for general performance I think Geekbench is okay.

We have gone from monstrous benchmarks like Winstone (remember that one?) to tiny ones that almost fit in L1 like CPUmark99.

I don't know a lot about Geekbench but it does seem to be cheap (free), small (doesn't junk up the computer) , and ubiquitous (lots of scores out there).

Can we name a few processors that outperform others in Geekbench but are obviously inferior in day-to-day usage? Those types of examples would be obvious failures for a benchmark.

This listing of performance seems pretty accurate to me.

Processor Benchmarks - Geekbench

 

[Henry swagger]

This is why SPEC is still favored.

You have Geekbench that abandoned being able to sort in GB4. In GB5 they stopped separating Int and FP results, and GB6 they added a niche instruction. Like do they understand their jobs?

This is from C&C for CPU-Z

So basically they are saying it's Dhrystone all over again. At least Dhrystone benchmarked pure performance of the ALU. CPU-Z is measuring what again?

They gave a Yellow star for effort. LOL!

Only geekbench 5 and specint17 are to be trusted more

 

[Henry swagger]

Intel Arrow Lake Refresh CPU Might Feature Upgraded NPU Leading To Larger Die Size

Intel might incorporate an upgraded NPU in its Arrow Lake Refresh CPUs for desktop & laptop platforms which will come at a cost.

wccftech.com

Arrow refresh will have a bigger npu 🤔

 

[AcrosTinus]

Is there any new news about AVX10.2 and the implementation into future generations ?
Can it be expected with the Panther ?

 

[Kepler_L2]

Is there any new news about AVX10.2 and the implementation into future generations ?
Can it be expected with the Panther ?

AFAIK:

Granite Rapids AVX10.1/512
Granite Rapids-D AVX10.1/256
Diamond Rapids and later AVX10.2/512
Nova Lake and later AVX10.2/256
Rogue River Forest and later AVX10.2/256

 

[Fjodor2001]

Intel Arrow Lake Refresh CPU Might Feature Upgraded NPU Leading To Larger Die Size

Intel might incorporate an upgraded NPU in its Arrow Lake Refresh CPUs for desktop & laptop platforms which will come at a cost.

wccftech.com

Arrow refresh will have a bigger npu 🤔

So 8P+32E+iGPU+Big NPU. Sounds nice. Would be lots of compute perf.