Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Jan Olšan]

New update again
View attachment 102797

I guess that means the actual clocks (during the +3//+15% benchmarking) were higher than that 4.7 GHz value.

 

[csbin]

WTF...

https://twitter.com/x/status/1811382416529055916

https://twitter.com/x/status/1810146335158333659

 

[Josh128]

I guess that means the actual clocks (during the +3//+15% benchmarking) were higher than that 4.7 GHz value.

lol, the 'tards over at WCCFTECH think Im Jaykihn.

 

[dullard]

You're really splitting hairs over .5% ST and 4% MT? The "actual data" was the same leaked slide we both saw last year and some warnings form leakers showing numbers from an ES2. I'm just repeating an oft-repeated summary of that slide (yes, MANY PEOPLE QUOTED THE 5%/20% NUMBERS), and your own guesstimations are insignificantly different. Nobody gives a darn about a delta of +.5% ST and -4% MT from a summary of a slide from last year. Nobody. You're arguing just to argue, stop.

Clearly, you didn't read my post. You were the one complaining that the leaked slide last year was optimistic, when in fact, it was about the exact same ST and MT gains as what we just saw in leaked results. If nobody cares, then why did you post that the leaked slide was optimistic? I fully agree that it is splitting hairs, thus you should edit or delete your post that the leaked slide was optimistic--because it wasn't optimistic.

Oh and, this is a free space. I stop posting when I want to stop posting. Not just because you were called out for being contradictory and can't stand to hear about it.

 

[dullard]

I'm a little unclear on something regarding that tweet.

So the 4.7/4.0 clocks were with PL1 & PL2 = 250W? If so, do we really expect the retail clocks to be much higher? 250W is already rather high.

A lot of the changes between engineering samples and production chips is that they have a chance to tweak areas with unwanted power leaks.

Plus what others have said. PL1 and PL2 are maximums for given time periods -- not the power that was actually used. The power actually used depends on the specific benchmark and specific cooling installed. CPUs only use 250W or more for any meaningful length of time when attached to a cooling system that can handle 250W or more.

 

[SteinFG]

WTF...

>Rumor: ARL-S Sales: December

2 months past october, the usual month. Not that crazy

 

[Josh128]

Unless something has gone horribly wrong, expectations for ARL-S should be approx 5.6-5.8 GHz ST boost clock, based on TSMCs current frequency ceiling (yes, N3 may be different than N5P/N4, but I doubt by much), +14% IPC (based on Lunar Lake presentation). So, + 11.5%- 14% absolute perf in ST vs 13900K, a few % less as you go up the stack to 14900KS.

MT should be really, really good based on Skymont gains + 3nm TSM process. Depending on what kind of true power limits it has, 48K-50K in performance mode in R23 is probably a safe, realistic expectation. Zen 5 9950X, on the other hand, appears that it will top out at 44K-45K range when given full PBO 230W PPT.

 

[dullard]

2 months past october, the usual month. Not that crazy

Other than Coffee Lake, Raptor Lake, and their respective refreshes, what chips did Intel launch in October? I'm just asking what makes a "usual month" to you.

 

[SteinFG]

Coffee Lake, Raptor Lake, and their respective refreshes [...] I'm just asking what makes a "usual month" to you.​

Exactly that ☝️

 

[SteinFG]

BTW Kopite says ARL-S is probably releasing in October

 

[dullard]

Exactly that ☝️

I ask since Sky Lake, Kaby Lake, and Comet Lake were all launched in August. While Haswell, Haswell Refresh, and Broadwell were all launched in June. Nahalem and Alder Lake in November. Then there are recent launches in April (Ivy Bridge), March (Rocket Lake), and December (Meteor Lake). That is, there isn't much of a pattern.

That said, I do think October is the goal.

 

[cebri1]

Other than Coffee Lake, Raptor Lake, and their respective refreshes, what chips did Intel launch in October? I'm just asking what makes a "usual month" to you.

Alder Lake was launched in early November, Raptor Lake and Refresh were in October. So three consecutive generations in early Q3.

 

[SiliconFly]

Well, now it’s clear that @jaykihn0’s +3% ST perf projection was completely off the mark.

If LNC has +3% ST perf at a meager 4.7GHz (that too an ES), >20% ST perf uplift is definitely within the realm of possibility for the top end sku like I mentioned before.

And contrary to @jaykihn0’s claims, the CPU-Z benchmark leak might actually be real.

 

[ondma]

Well, now it’s clear that @jaykihn0’s +3% ST perf projection was completely off the mark.

If LNC has +3% ST perf at a meager 4.7GHz (that too an ES), >20% ST perf uplift is definitely within the realm of possibility for the top end sku like I mentioned before.

Look at post 9897. That contains the latest info from that poster. He says that his chip was "unlocked", so not restrained to ES2 speeds (i.e. 4.7 ghz). However he says he had no way to verify the actual frequency, so a very sketchy post overall. I would not be excited, but IMO anything 10% or over is good for ST performance uplift. 20% or higher is definitely a pipe dream. Anything 5% or less like the leaks are suggesting, though, is a disaster.

 

[Saylick]

BTW Kopite says ARL-S is probably releasing in October

Ehhh? That's not my interpretation.

 

[majord]

IF I was forced to make a bet, Id say it will top out at 5.2 to 5.3ghz , but I think theres too many small variables still. One thing seems almost certain , that SC perf increase will be less than IPC / perf/clock increase , so a freq regression seems inevitable . It also makes sense given the transition to TSMC

 

[Josh128]

IF I was forced to make a bet, Id say it will top out at 5.2 to 5.3ghz , but I think theres too many small variables still. One thing seems almost certain , that SC perf increase will be less than IPC / perf/clock increase , so a freq regression seems inevitable . It also makes sense given the transition to TSMC

No way man. Desktop on 3nm TSM should clock every bit as good as 5/4nm TSM. Surely its not hitting 6.2, but I'd put big money that its likely to clock right up there with Zen 4 and 5. 5.6-5.7 for sure, and maybe more.

 

[Goop_reformed]

No way man. Desktop on 3nm TSM should clock every bit as good as 5/4nm TSM. Surely its not hitting 6.2, but I'd put big money that its likely to clock right up there with Zen 4 and 5. 5.6-5.7 for sure, and maybe more.

5.6-5.7ghz for a core that wide? Doesn't bode well for power consumption

 

[H433x0n]

5.6-5.7ghz for a core that wide? Doesn't bode well for power consumption

Huh? Do you even know if it’s appreciably wider than Zen 5?

 

[Goop_reformed]

Huh? Do you even know if it’s appreciably wider than Zen 5?

It is much wider than zen 5 and zen 5 is not particularly wide at all. Golden Cove family of cores are even wider and look at how many problems they have.

 

[H433x0n]

It is much wider than zen 5 and zen 5 is not particularly wide at all. Golden Cove family of cores are even wider and look at how many problems they have.

Unless you have inside information you can’t possibly know that since we don’t know Zen 5 core resources other than surface information such as it being a 4x2 decode, which is the same width as Lion Cove.

 

[Goop_reformed]

Unless you have inside information you can’t possibly know that since we don’t know Zen 5 core resources other than surface information such as it being a 4x2 decode, which is the same width as Lion Cove.

Let me put it this way. Intel cores are bloated, and are getting bloated. The trend continues for the foreseeable future

 

[H433x0n]

Let me put it this way. Intel cores are bloated, and are getting bloated. The trend continues for the foreseeable future

Cool, can you share the details of Zen 5’s ROB, uOP cache, ALU count, register file size, etc?

 

[Goop_reformed]

Cool, can you share the details of Zen 5’s ROB, uOP cache, ALU count, register file size, etc?

Past behavior is the best predictor for future outcomes.

 

[DavidC1]

Cool, can you share the details of Zen 5’s ROB, uOP cache, ALU count, register file size, etc?

You know David Huang says it cut uOP cache sizes to Zen 3 levels and even PRF sizes right? Hence the 16% gains despite big changes elsewhere.

Let me put it this way. Intel cores are bloated, and are getting bloated. The trend continues for the foreseeable future

Totally agree on this one. They will be replaced.