Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Wolverine2349]

Raptorlake desktop is 7% faster than Raptorlake mobile, which will make up for the difference.

Consider that it'll run laps around Zen 5 mobile for battery life, so even if it had 7% deficit, no one buying it will care.

Is Raptor Lake desktop 7% than Raptor Lake mobile when clock normalized as in IPC?

 

[DavidC1]

Is Raptor Lake desktop 7% than Raptor Lake mobile when clock normalized as in IPC?

Ok, if it wasn't normalized, what would be the point of saying that Desktop is 7% faster than Mobile?

The gap existed since when laptops used same architecture chips as desktop. It has much more strict power saving features, it goes out of power management states slower(thus making all IO slower, such as interconnects, DMI, and drives), and it has memory with looser timings.

This is why I don't believe Meteorlake has a Tile penalty, nor Redwood Cove is slower anymore. Arrowlake will be 6-7% faster purely because laptop vs desktop, not uarch, nor better tiles.

 

[Wolverine2349]

Ok, if it wasn't normalized, what would be the point of saying that Desktop is 7% faster than Mobile?

The gap existed since when laptops used same architecture chips as desktop. It has much more strict power saving features, it goes out of power management states slower(thus making all IO slower, such as interconnects, DMI, and drives), and it has memory with looser timings.

This is why I don't believe Meteorlake has a Tile penalty, nor Redwood Cove is slower anymore. Arrowlake will be 6-7% faster purely because laptop vs desktop, not uarch, nor better tiles.

Yeah your right as yeah laptops have much lower CPU clocks than desktops as such. Should haver thought of that.

So of course 7% faster IPC clock normalized.

 

[poke01]

Desktop Lion cove looks good. 15%-25% IPC

 

[Goop_reformed]

View attachment 102927
Desktop Lion cove looks good. 15%-25% IPC

"projected" and it doesn't look very good considering his intel projected performance has been all over the place. This has been the 5th revision I think.

 

[mikk]

QS week34 he says now.

ARL-S 8+16 die QS switched to ww34 bahahahaha

Terrible timing for the December rumor (which is 100% not true).

Late October.

6+8 die (which will be used in non-k SKUs alongside 8+16) is still targeting ww49.

https://twitter.com/x/status/1811877506582012006

 

[Henry swagger]

View attachment 102927
Desktop Lion cove looks good. 15%-25% IPC

Lets hope N3B clocks high as intel 7

 

[Tup3x]

Lets hope N3B clocks high as intel 7

I hope this time it would use reasonable amount of power.

 

[cebri1]

The issue for ARL is the RPL PR disaster. Intel needs to come up with a very good explanation and testable solution + changes in Quality Assurance or high end gamers won’t trust them.

 

[511]

View attachment 102927
Desktop Lion cove looks good. 15%-25% IPC

15-25 is way too much IPC range it would turn out to be 14-19% 14% is the minimum baseline MLID Refresh spec

 

[AMDK11]

Ok, if it wasn't normalized, what would be the point of saying that Desktop is 7% faster than Mobile?

The gap existed since when laptops used same architecture chips as desktop. It has much more strict power saving features, it goes out of power management states slower(thus making all IO slower, such as interconnects, DMI, and drives), and it has memory with looser timings.

This is why I don't believe Meteorlake has a Tile penalty, nor Redwood Cove is slower anymore. Arrowlake will be 6-7% faster purely because laptop vs desktop, not uarch, nor better tiles.

What do you mean by better tiles?

ArrowLake-S (LGA1851) because it is Desktop will definitely have faster (higher clocked or even wider) connections between tiles, a higher clocked RAM controller, ring bus, etc.

I am sure that this will translate into a practically higher achievable IPC.

As for changes in the micro architecture of the cores, the engineer said that LionCove in ArrowLake and LunarLake differs in several respects, so nothing has been decided yet.

Intel emphasizes that on average +14% higher IPC LionCove is for the LunarLake variant, so translating this to ArrowLake-S does not make much sense.

Intel officially, and also from statements by LionCove engineers, has implemented a completely new PBU("up to 8x
larger prediction block") block with new algorithms, which suggests that individual variants may have a smaller PBU (LunarLake).

 

[TwistedAndy]

Jaykihn has posted the Arrow Lake block scheme:

https://twitter.com/x/status/1812111025291796737

It looks very similar to Meteor Lake

 

[reb0rn]

Can anyone speculate how would it behave with AVX512 will Arrow Lake have AVX10 more so compared with zen5, I guess E cores still will limit a lot from full AV512 support or not so?

 

[ErichZannMusician]

Can anyone speculate how would it behave with AVX512 will Arrow Lake have AVX10 more so compared with zen5, I guess E cores still will limit a lot from full AV512 support or not so?

ARL doesn't have AVX10. AVX10 support is supposed to be introduced with Granite Rapids.

 

[DavidC1]

Intel officially, and also from statements by LionCove engineers, has implemented a completely new PBU("up to 8x
larger prediction block") block with new algorithms, which suggests that individual variants may have a smaller PBU (LunarLake).

I explained it before, but people didn't read it.

Execution determines the rest, and Meteorlake was poor execution due to numerous delays. Same high end setup can have differing performance targets. So Arrowlake could have better Tiles.

However,

expecting anything material(1-2%) is IMO hopium. Arrowlake will be faster purely because it's on a desktop platform. RPL-H vs RPL-S comparisons show that Meteorlake has NO tile penalty. Also you are taking 8x prediction too seriously. It is a subsection that's not significant. So what, you think LNL has 1x and ARL suddenly has 8x? The increase is 8x because they saw the previous one as being hopelessly deficient.

Sorry this is denial that Intel/AMD gains are low, which prior to Computex reveal almost NOONE expected. Yet they did.

QS week34 he says now.

20A die for WW49 is Jan/Feb by that timeline. That's pretty good. From Late-2023 Intel 4 too Early 2025 for Intel 20A. Improved execution is needed both on the process and design side is needed to achieve this. I assume we'll see Clearwater Forest in late 2025 and Pantherlake in early 2026.

 

[DavidC1]

I hope this time it would use reasonable amount of power.

It's not power that's the issue. This is reminiscent of Pentium III 1.13GHz. They pushed it too far. If that's actually the case, 6GHz even in single thread is not a realistic clock.

Arrowlake's supposed 5.7GHz may be too high too.

@uzzi38 The P core architecture needs to be scrapped with a new one that backs clocks to 4.5GHz range but with higher performance per clock. Reduced pipeline stages back to 14-15, eliminating the need for complex solutions like uop caches.

If you assume Lion Cove is Prescott then we're still several years away from a proper replacement.

 

[AMDK11]

expecting anything material(1-2%) is IMO hopium. Arrowlake will be faster purely because it's on a desktop platform. RPL-H vs RPL-S comparisons show that Meteorlake has NO tile penalty. Also you are taking 8x prediction too seriously. It is a subsection that's not significant. So what, you think LNL has 1x and ARL suddenly has 8x? The increase is 8x because they saw the previous one as being hopelessly deficient.

NO. LunarLake may have a LionCove variant with, for example, a 4-5x larger PBU block and ArrowLake with an 8x larger PBU block.

Note that Intel never stated how much it improved the PBU, only that it was improved.


If, as you claim, these 8x referred to a subset of PBU parts, Intel would say that e.g. buffers, algorithms or other queues are 8x larger/more complex. They literally emphasize here that the entire PBU block (prefetch + branch prediction) is 8x larger.

I stick to this and what you write is only your interpretation or over-interpretation of official data.


The PBU block is extremely important, so I tend to take literally the statement of Intel engineers who claim that the PBU block is 8 times larger and the algorithms contained in it are fundamentally new. They also claim that to better utilize the new PBU, request throughput to L2 has been increased by a factor of 3, and the PBU block itself can now fetch 128 bytes per cycle instead of 64.

 

[mikk]

I explained it before, but people didn't read it.

Execution determines the rest, and Meteorlake was poor execution due to numerous delays. Same high end setup can have differing performance targets. So Arrowlake could have better Tiles.

However,

expecting anything material(1-2%) is IMO hopium. Arrowlake will be faster purely because it's on a desktop platform. RPL-H vs RPL-S comparisons show that Meteorlake has NO tile penalty. Also you are taking 8x prediction too seriously. It is a subsection that's not significant. So what, you think LNL has 1x and ARL suddenly has 8x? The increase is 8x because they saw the previous one as being hopelessly deficient.

RPL-H has 5% better IPC than MTL-H, from where does it come from if not from the tiles and Soc IMC?

 

[DavidC1]

RPL-H has 5% better IPC than MTL-H, from where does it come from if not from the tiles and Soc IMC?

Not according to Geekerwan.

It is extremely difficult to normalize on laptops anyway. Unless we have a desktop Meteorlake part, you'll NEVER get the full picture.

Are you willing to bet the farm on your claims?

I stick to this and what you write is only your interpretation or over-interpretation of official data.

No, I base it on my experience. And you literally enlarged the entire BPU block in the hypothetical picture a while back, which would make zero sense as it would enter diminishing returns very quickly, so it's obvious that it's a subsection, just like Battlemage got 12.5x XI boost.

If they did increase the Branch prediction size by 8x, it would also confirm that the P core team is close to being braindead, because they would get a fraction of a fraction of the increase in resources.

Why after increasing it little by little would they decide to boost everything by 8 times? So we have a 60-70K sized BTB now? It's ridiculous. Also if increasing it by 4-5x improved it by a total of 14%, going to 8x won't get you much.

This is like arguing Zen 5 is 15-20% in the crowd of people that believed 30% is too low of a figure.

 

[AMDK11]

No, I base it on my experience. And you literally enlarged the entire BPU block in the hypothetical picture a while back, which would make zero sense as it would enter diminishing returns very quickly, so it's obvious that it's a subsection, just like Battlemage got 12.5x XI boost.

If they did increase the Branch prediction size by 8x, it would also confirm that the P core team is close to being braindead, because they would get a fraction of a fraction of the increase in resources.

Why after increasing it little by little would they decide to boost everything by 8 times? So we have a 60-70K sized BTB now? It's ridiculous. Also if increasing it by 4-5x improved it by a total of 14%, going to 8x won't get you much.

This is like arguing Zen 5 is 15-20% in the crowd of people that believed 30% is too low of a figure.

I think there's a difference between saying Battlemage is 12.5 times faster at something and saying the PBU block is 8 times larger.

Otherwise they would say that the PBU is completely new with new algorithms or something like that and not that the PBU block is 8 times larger.

Of course, more details and a photo of the structure will dispel any doubts.

 

[mikk]

Not according to Geekerwan.

It is extremely difficult to normalize on laptops anyway. Unless we have a desktop Meteorlake part, you'll NEVER get the full picture.

Are you willing to bet the farm on your claims?

I compare SKUs with the same ST Boost and it's a few percent slower. MTL never could reach the same Geekbench ST scores for example. Compare 165H with 1360P, there is a 100 points/4% ST difference from the best results. From where does the decline come from?

​

 

[StinkyPinky]

This looks to be an upcoming lunar lake laptop

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[Ghostsonplanets]

https://twitter.com/x/status/1812538246414692362

"Because of external nodes, Intel is unable to upgrade the LGA1700 as a whole, making it difficult for ARL to engage in a price war.
Due to the cancellation of PTL-S, RPL will continue to be the main shipping force. Resolving the issue of RPL would be a very significant problem."

If I'm reading correctly, Kopite is saying that Intel next-gen parts are expensive and they still expect RPL to be the bulk of sales in the foreseeable future.

It's Kopite, but I'm not sure how reliable he is for Intel at all.

 

[Saylick]

https://twitter.com/x/status/1812538246414692362

"Because of external nodes, Intel is unable to upgrade the LGA1700 as a whole, making it difficult for ARL to engage in a price war.
Due to the cancellation of PTL-S, RPL will continue to be the main shipping force. Resolving the issue of RPL would be a very significant problem."

If I'm reading correctly, Kopite is saying that Intel next-gen parts are expensive and they still expect RPL to be the bulk of sales in the foreseeable future.

It's Kopite, but I'm not sure how reliable he is for Intel at all.

That seems to jive with @adroc_thurston’s claim that RPL is cheap and on a depreciated process node, so it’ll remain the backbone of Intel’s volume shipments. But yeah, if true, it’s a train wreck waiting to happen if they can’t find a solution for instability issues that upper end RPL faces.

Also, this:

https://twitter.com/x/status/1812546596938322101

 

[Doug S]

https://twitter.com/x/status/1812538246414692362

"Because of external nodes, Intel is unable to upgrade the LGA1700 as a whole, making it difficult for ARL to engage in a price war.
Due to the cancellation of PTL-S, RPL will continue to be the main shipping force. Resolving the issue of RPL would be a very significant problem."

If I'm reading correctly, Kopite is saying that Intel next-gen parts are expensive and they still expect RPL to be the bulk of sales in the foreseeable future.

It's Kopite, but I'm not sure how reliable he is for Intel at all.

It isn't clear whether he's implying it is due to the cost of those external nodes or the availability. TSMC's N3B capacity is limited, N3E is where the volume is. For either issue the solution would have been for Intel to port to N3E, but for whatever reason they chose not to. So if that means RPL has to continue on longer as a result that's kind of their fault, since I doubt TSMC was forcing them to choose/stick with N3B.