Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Aeonsim]

Nope. First off, HT loss in ARL isn't 30%. It's upto 30% on very specific cases. Generally, it's around 15% (and maybe even upto 20% on occasions). But when HT is removed from a core, ST gets a solid boost which offsets the HT loss. So, the effective loss due to lack of HT is not that much. Instead, we can expect better ST boost than normal. Thats the reason Lion Cove dropped HT.

In short, ARL is expected to post a solid Geekbench 6 MT score compared to previous gen and compared to competition. All those low MT perf numbers that are projected are pretty much fake/rumors.

It's very easy to test this, simply run your fav multi-core benchmarks, reboot, enter bios, disable hyperthreading. Load into windows run your fav multithreaded benchmarks.

Note GB isn't great for multi-core testing so use something more intense that runs for a while.

 

[AcrosTinus]

I believe Intel has something special on their hands:

• A new P core designed with industry standard tools for rapid iteration
• A new P core and E core layout around the ringbus
• dedicated PCIe5x4 lane for faster storage
• new caching structure on the P cores
• Skymont being on Raptor Cove performance level when on ring
• Lion Cove with still secret changes on the desktop version
• IGPU with the industry best encoders and decoder for 4:2:2 10bit

I will give Intel the benefit of the doubt, 2 machines need an upgrade and if they hit my low bar of being 10% faster but coolable, I am fine with it. I want to get rid of all those 420mm and 360mm AIO i deploy.

If they fail to meet this bar... I will wait for AMDs active substrate CPUs with COWOS and such and hop over.

 

[majord]

ARL 5.4ghzP 4.6ghzE should do 47K+ R23 MT going by current Intel claims about Lion cove and Skymont IPC.

you think they gonna hit 5.4Ghz all core load? Seems a bit wishful thinking, but we'll see. I guess 347A will help 🔥

 

[CakeMonster]

• A new P core designed with industry standard tools for rapid iteration

I remember when we had rapid iteration of the architecture. I loved reading the AT architecture overviews when Intel tweaked the architecture on a yearly basis, from Core 2 up to Skylake. It felt like we were going somewhere, even if the changes weren't always huge.

 

[AcrosTinus]

I remember when we had rapid iteration of the architecture. I loved reading the AT architecture overviews when Intel tweaked the architecture on a yearly basis, from Core 2 up to Skylake. It felt like we were going somewhere, even if the changes weren't always huge.

Those times might be coming back, the competition is too strong for that to not be the case. Qualcomm, Apple, AMD everyone wants a piece of the computing pie and Intel despite their failures still has the capacity to excel.
Furthermore I also think that SYCL/oneAPI is a good alternative to CUDA. Intel has the tech to compete, it might not always be the best but it is still high tech.

 

[Geddagod]

you think they gonna hit 5.4Ghz all core load? Seems a bit wishful thinking, but we'll see. I guess 347A will help 🔥

That's the current rumor according to Raichu. 5.7GHz peak.
I just want to point out, the 14900k did 5.7GHz all P core boost. And it was consuming a peak of ~280 watts in nT workloads. The 13900k did 5.5GHz all core boost.

 

[dullard]

Seems like power limits also are going up.
Must say this don't fill me with confidence..

Once again your data and your conclusions aren't quite in sync. (1) Your chart doesn't include Raptor Lake Refresh. (2) That is absolute max allowed -- not what will actually be used.

On your table, ICCMax for Arrow Lake-S (347 A) is actually down from Raptor Lake Refresh (400 A). Here is Anandtech's quote on Raptor Lake Refresh: "Intel has added a new 'Extreme' Power Delivery Profile, implemented through the firmware on capable boards, and increases the ICCMax to 400 A, up from the default 307 A value."

Intel Core i9-14900K, Core i7-14700K and Core i5-14600K Review: Raptor Lake Refreshed

www.anandtech.com

As for actual power used in setups that aren't in the 'Extreme' category, the latest rumor that I have seen shows PL2 and PL4 are DOWN for Arrow Lake:

• Intel Raptor Lake 125W (PL1/PL2/PL4) 24 Core SKU - 125W / 253W / 420W
• Intel Arrow Lake 125W (PL1/PL2/PL4) 24 Core SKU - 125W / 177W / 333W

Alleged Intel Arrow Lake-S CPU Power Limits Revealed: 125W PL1, 177W PL2, 333W PL4 For 8+16 Core Unlocked SKU

Alleged power limits of Intel's Arrow Lake-S Desktop CPU featuring 8 P-Cores and 16 E-Cores have been revealed by Darkmont.

wccftech.com

 

[mikk]

New Geekbench 6 score from Ultra 7 256V. This is the best MT score from LNL so far.

LENOVO 21NSSIT021 - Geekbench

Benchmark results for a LENOVO 21NSSIT021 with an Intel Core Ultra 7 256V 2.20GHz processor.

browser.geekbench.com

 

[MarkPost]

That's the current rumor according to Raichu. 5.7GHz peak.
I just want to point out, the 14900k did 5.7GHz all P core boost. And it was consuming a peak of ~280 watts in nT workloads. The 13900k did 5.5GHz all core boost.

and consequently we have the Raptor Lake debacle

 

[Henry swagger]

Once again your data and your conclusions aren't quite in sync. (1) Your chart doesn't include Raptor Lake Refresh. (2) That is absolute max allowed -- not what will actually be used.

On your table, ICCMax for Arrow Lake-S (347 A) is actually down from Raptor Lake Refresh (400 A). Here is Anandtech's quote on Raptor Lake Refresh: "Intel has added a new 'Extreme' Power Delivery Profile, implemented through the firmware on capable boards, and increases the ICCMax to 400 A, up from the default 307 A value."

Intel Core i9-14900K, Core i7-14700K and Core i5-14600K Review: Raptor Lake Refreshed

www.anandtech.com

As for actual power used in setups that aren't in the 'Extreme' category, the latest rumor that I have seen shows PL2 and PL4 are DOWN for Arrow Lake:

Alleged Intel Arrow Lake-S CPU Power Limits Revealed: 125W PL1, 177W PL2, 333W PL4 For 8+16 Core Unlocked SKU

Alleged power limits of Intel's Arrow Lake-S Desktop CPU featuring 8 P-Cores and 16 E-Cores have been revealed by Darkmont.

wccftech.com

Shut him down real quick 🥇

 

[Elfear]

Shut him down real quick 🥇

Yes, that's exactly what we want in a discussion/speculation thread when a rumor is posted...🙄

Thread has been fairly civil (including Detox and Dullard's posts) so not sure why you felt the need to post that.

 

[DavidC1]

Shave 1000-1500 pts off from that if you want to compare at 15 W, and even then LNL should score 14K in CB23 MT.

Which is just a random guess on your part. We know from the frequency curve Meteorlake drops off in performance quite drastically. So if it's 7K, then LNL is 10.5K.

I believe Intel has something special on their hands:

• A new P core designed with industry standard tools for rapid iteration

"Rapid iteration" nonsense has been paraded by Intel since they introduced the ringbus with Sandy Bridge. The reality is these projects are immensely complex and increase in complexity every generation that new different methodologies are needed just to compensate for increase in complexity.

It looks like Granite Rapids core has quite nice changes, but it's also part of the move to intel 3 and delays quoted by Pat so I would not attribute it entirely to the new design process either. Previously it took them more than a year to add extra L2 cache and the 512-bit FPU, so if it indeed comes with 8-way decoder and backend, it is an improvement.

Don't expect client to have big changes though.

• Lion Cove with still secret changes on the desktop version

There's nothing secret about it other than the 0.5MB extra L2. In fact before the Computex reveal people said Lunarlake used Lion Cove+ and had extra changes over Lion Cove on Arrowlake. Now people are saying the opposite? I say just pure denial over the mere 14% gains being lower than expected. I don't see the AMD camp in denial over 16% even though most were certain it would be in upwards of 30%?

 

[mikk]

If the leaked CB23 scores are from Jaykinn, then it is likely that those are outdated information.

Because the 165U scores 10.5K in CB23 mT with a 21 W PL1.

Shave 1000-1500 pts off from that if you want to compare at 15 W, and even then LNL should score 14K in CB23 MT.

But yes, all this is irrelevant. The point is that Lion Cove, even with acceptable levels of IPC uplift, will have no problem keeping up with the competition at similar clock speeds.

MTL-U at 15W does 6681 points in CB R23 according to Jaykihn.

 

[SiliconFly]

... are immensely complex and increase in complexity every generation that new different methodologies are needed just to compensate for increase in complexity. ...

Not necessarily. The purpose of their new methodologies is to reduce turn around time. Modular design divides a large IP into smaller IP blocks which in turn significantly reduces design, development & validation times. And also, it enables IP reuse. For example, by reusing the SoC tile in ARL, they're significantly reducing the time, money and resources required otherwise to build a new one. Thats a large amount of savings. Also, a smaller IP block helps them iterate faster. Not the other way around.

 

[AcrosTinus]

I have hope, my expectations are quite low.
I want 10% better performance in general compute and lower cooling requirements as well as a word from Intel regarding the defects problem of 13th and 14th gen.

If they can deliver I am happy, this is not a cake they are baking.
The people at Intel are doing super complex work, so I have respect even if things don't pan out.

 

[SiliconFly]

... so I have respect even if things don't pan out.

On the contrary, I think the idiots at Intel were well aware of the defect already, but it appears they've grossly underestimated the scale of its impact. It's just Intel desperately trying to match/outdo competition at the expense of customers. Just plain bad. It is very important that they provide a fix asap or do a full recall, otherwise everyone's gonna spit in their face sooner or later. I'm just waiting for Pat to get back to his senses before it's too late.

 

[AcrosTinus]

On the contrary, I think the idiots at Intel were well aware of the defect already, but it appears they've grossly underestimated the scale of its impact. It's just Intel desperately trying to match/outdo competition at the expense of customers. Just plain bad. It is very important that they do a full recall, otherwise everyone's gonna spit in their face sooner or later. I'm just waiting for Pat to get back to his senses before it's too late.

I hope you are exaggerating, these are not idiots. Most of them have advanced degrees. I know two intel engineers, I have never met people with that much passion for tech.

In a huge company like that many decision are out of the hand of people in the lower ranks or RND level. I work in a larger company and get tons of restrictions even if solutions to problems seem so obvious.

 

[SiliconFly]

I hope you are exaggerating, these are not idiots. Most of them have advanced degrees. I know two intel engineers, I have never met people with that much passion for tech.

In a huge company like that many decision are out of the hand of people in the lower ranks or RND level. I work in a larger company and get tons of restrictions even if solutions to problems seem so obvious.

I'm talking more about their ruthless marketing department than their engineers. It's now common knowledge that their RPL & RPL-R K-series is a disaster. They're just ignoring the problem and refusing to respond. I like Intel, but like I always say, it's time to call a spade a spade.

 

[AcrosTinus]

I'm talking more about their ruthless marketing department than their engineers.

I agree then.

 

[DavidC1]

Not necessarily. The purpose of their new methodologies is to reduce turn around time. Modular design divides a large IP into smaller IP blocks which in turn significantly reduces design, development & validation times. And also, it enables IP reuse.

For us consumers and users of the said product it makes zero difference. I don't see next generation coming earlier do you? Nor the gains greater than before? It requires MORE work today to get LESS benefits.

One benchmark Intel used in their testing to showcase the advances of their processors over the years was used for designing ever more complex designs. The gains in that benchmark over generations were noticeably lower than the increase in complexity over the same time. More work, less benefit!

In the black box scheme of things all the fancy terminologies such as "methodologies", "modular", "tiles", "disaggregation", "chiplets" didn't make an ounce of difference in more iterations, nor the timeline between generations become shorter.

 

[SiliconFly]

... such as "methodologies", "modular", "tiles", "disaggregation", "chiplets" didn't make an ounce of difference in more iterations, nor the timeline between generations become shorter.

If not for these "terminologies", the timeline between generations will become even more longer.

... It requires MORE work today to get LESS benefits. ...

In an ever changing world, this statement has always remained a constant since the beginning of time.

I don't see next generation coming earlier do you?

They're just starting over after a major screw up. Things aren't gonna change in a day. I expect Intel to iterate faster with their core designs in the future that before.

 

[DavidC1]

If not for these "terminologies", the timeline between generations will become even more longer.

Exactly, and don't expect it to become shorter. "Revolutionary" advancements are merely there to enable continued progress, not some radical step function increase in development.

I'm saying to outsiders it did nothing to make it shorter. Therefore, they could call it what they want, but doesn't really matter.

 

[DrMrLordX]

HT "threads" are just emulation. The loss of thread count won't bring MT perf down by much cos each physical core tends to gain ST perf when HT is removed which compensates well.

That's only true for workloads that can keep the pipeline full. Gaps or stalls make SMT shine.

N3B has more mask layers and has less performance than n3E.. intel will use n3E for arrow refresh i think 🤔

. . . if they can afford the capacity.

 

[ErichZannMusician]

MTL-U at 15W does 6681 points in CB R23 according to Jaykihn.

That is somewhat vague. Does 15 W mean PL1=PL2=15W or PL2>PL1=15W?

 

[mikk]

That is somewhat vague. Does 15 W mean PL1=PL2=15W or PL2>PL1=15W?

PL1+PL2= 15W