Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[TESKATLIPOKA]

Pantherlake does have the LPE core again. I'm not sure if it's with other cores or in the PCD.

Then let's hope It's at same as E cores.

 

[ondma]

Intel reportedly planning 8-core Core Ultra 3 205/215 Arrow Lake desktop processors - VideoCardz.com

Intel Core Ultra 3 in Arrow Lake desktop Only 8 cores. We have an update on the Arrow Lake desktop series from OneRaichu. The previous report didn’t include any details about low-end processors within the Core Ultra 3 tier, suggesting only Core Ultra 5, 7, and 9 were expected. However, it...

videocardz.com

A 4P+4E Core Ultra 3 would be amazing value for the sub $150 market while demolishing anything AMD has to offer in that price range.
Should offer a big MT performance boost over previous gen as well, and gaming performance will be more than good enough for that price range.

I dont know about gaming. Current i3 is 4P with hyperthreading. That is indeed pretty decent for gaming. I dont think 4 slightly improved P cores without hyperthreading would perform as well. It would only be a good design if Intel could somehow manage to utilize the E cores for gaming. It WOULD probably be nice for budget application performance.

 

[Philste]

-Lunarlake will achieve fantastic battery life with just two core types. Why does Pantherlake add LPe again?

You are mixing things up. LNLs 2 core types ARE P and LPe. PTL just adds 8 normal E-Cores to scale multithread. Makes sense for them to keep the general LNL, which means all cores on one Tile, it just moves out the iGPU because it gets quite big eith 1536 Celestial ALUs.

 

[511]

Then let's hope It's at same as E cores.

It's simular LP-E as LNL probably based on DarkMont

 

[KompuKare]

I dont know about gaming. Current i3 is 4P with hyperthreading. That is indeed pretty decent for gaming. I dont think 4 slightly improved P cores without hyperthreading would perform as well. It would only be a good design if Intel could somehow manage to utilize the E cores for gaming. It WOULD probably be nice for budget application performance.

Short of Intel profiling all threads, I think only the application itself could do that.

Some kind of request when spawning a thread to the kernel saying "this thread is okay with 60% of the performance of my main thread".

However, if the spawned thread cannot be exactly predicted - maybe handling NPCs which can scale, or other players in a multi player game - then how the developers would have to specify something like "this thread is okay with 60% performance of the main, expect when X, Y or Z is the case - scrap that: give a full 100% performance core"

Or am I missing something?

 

[Hitman928]

Another Intel mistake. Cancelling hybrid Falcon Shores.

AMD on MI300 announced that it's the fastest product to reach $1 billion in revenue. In this dire time, $1 billion could have been a boon to Intel. I doubt it's just "AIeee" why companies are snapping up MI300. Combined high performance CPU/GPU has many other uses and it's a unique product.

Along the way of "saving" money Intel will inevitably make more long term mistakes. Sure, maybe when all 110K employees are gone and the company goes down they'll save $20 billion per year!

https://cdn.wccftech.com/wp-content/uploads/2024/03/AMD-5th-Gen-EPYC-Turin-Zen-5-Zen-5C-CPU-Family-Up-To-160-Cores.jpeg

EPYC Turin ofrecerá entre 128 núcleos y 192 núcleos

Se está filtrando una hoja de ruta y unas especificaciones sobre los futuros AMD EPYC Turin, Turin-X, Turin Dense, Turin AI y mas.

www.profesionalreview.com

The 192 core Turin Dense and 128 core Turin are both 500W.

Seems to use MLID as the source. Could be true, but I’m going to wait for something more official.

 

[mikk]

Pantherlake does have the LPE core again. I'm not sure if it's with other cores or in the PCD.

It has three active tiles: GPU, Compute/NPU, PCD or Platform Controller Die. It has two additional tiles but they are passive and for structural support.

There is no room for a full LPE cluster, the PCD in PTL is just 3 mm² bigger which makes sense given that H type of SKUs usually have a little more connectivity under the hood.

 

[jpiniero]

Another Intel mistake. Cancelling hybrid Falcon Shores.

AMD on MI300 announced that it's the fastest product to reach $1 billion in revenue. In this dire time, $1 billion could have been a boon to Intel. I doubt it's just "AIeee" why companies are snapping up MI300. Combined high performance CPU/GPU has many other uses and it's a unique product.

AMD's product is decently competitive... maybe even more than that in FP64.

Intel... not so much.

I'd agree that it would be a mistake to give up on HPC but you do need a competitive product to get sales.

 

[DavidC1]

Seems to use MLID as the source. Could be true, but I’m going to wait for something more official.

And the other is from a twitter source which shows even the 160 core Turin Dense has 500W TDP. The TDP has been said by leaders way before that leak.

While the comments he makes are often nonsense, the slides have been more often than not correct. Like the infamous one that proved Zen 5 isn't 32%, but 10-15%.

You are mixing things up. LNLs 2 core types ARE P and LPe.

You are making a distinction when there's none. Lunarlake's core serves both purpose, because it's well implemented and thus can scale, serving both LPE's role and the traditional E's role. The top Lunarlake chip has 5.1GHz P core Turbo and 3.7GHz E core Turbo, practically same as Meteorlake's regular E core.

Pantherlake does the unnecessary thing of adding a separate LPE on TOP of that. I assume the implementation should be better than the atrocious one in Meteorlake, but I would still hand the win to Lunarlake.

 

[KompuKare]

AMD's product is decently competitive... maybe even more than that in FP64.

Intel... not so much.

I'd agree that it would be a mistake to give up on HPC but you do need a competitive product to get sales.

Do we have any idea if overall Intel lost money on Aurora? I know it was very late, so if they lost of money maybe they threw in the towel?

 

[OriAr]

I dont know about gaming. Current i3 is 4P with hyperthreading. That is indeed pretty decent for gaming. I dont think 4 slightly improved P cores without hyperthreading would perform as well. It would only be a good design if Intel could somehow manage to utilize the E cores for gaming. It WOULD probably be nice for budget application performance.

Gaming would utilize the E cores just fine, just like it utilizes them now and how it utilizes HT threads.
Games can't differentiate between P and E cores, that's the job of the scheduler/thread director, I am not even sure whether games can differentiate between real cores and HT threads, so I don't expect game engines to be suddenly able to differentiate between P and E cores.

 

[Hitman928]

And the other is from a twitter source which shows even the 160 core Turin Dense has 500W TDP. The TDP has been said by leaders way before that leak.

While the comments he makes are often nonsense, the slides have been more often than not correct. Like the infamous one that proved Zen 5 isn't 32%, but 10-15%.

You are making a distinction when there's none. Lunarlake's core serves both purpose, because it's well implemented and thus can scale, serving both LPE's role and the traditional E's role. The top Lunarlake chip has 5.1GHz P core Turbo and 3.7GHz E core Turbo, practically same as Meteorlake's regular E core.

Pantherlake does the unnecessary thing of adding a separate LPE on TOP of that. I assume the implementation should be better than the atrocious one in Meteorlake, but I would still hand the win to Lunarlake.

Like I said, could very well be true, but I prefer to wait for more official sources.

 

[Philste]

The top Lunarlake chip has 5.1GHz P core Turbo and 3.7GHz E core Turbo, practically same as Meteorlake's regular E core.

Pantherlake does the unnecessary thing of adding a separate LPE on TOP of that.

Lunar Lakes E-Cores are not on the ring, so they are LPE-Cores. Of course they are way more capable than MTLs, but they still are the ones in use when the ring is turned off. PTL reuses this design and puts 8 additional E-Cores on the ring. PTL adds E Cores, not LPE-Cores. ARL Desktop is said to have 4.6GHz allcore for Skymont on all SKUs, so I guess mobile will also have like 4.3GHz. So 3.7GHz could very well be the standard LPE Frequency.

 

[Tup3x]

I wonder if no HT actually ends up improving the gaming performance more than ipc improvements.

 

[Tigerick]

Guys, I have compiled the upcoming Intel roadmap in the table below. Most of the information is known, so no surprise here. My source still could not tell me how many cores NVL going to have. Nor which process Intel going to use. Desktop version of NVL should launch in Q4 2026 with HX version launching in Q1 2027.

There is one document talk about PTL-MX but he is not sure can consider as LNL successor.

Again, this is Intel we are talking about, roadmap could change. I will update the table in case anything changes...

Year		2024 -25	2025 - 26	2026 - 27
Desktop		Arrow Lake S	ARL-S Refresh	Nova Lake S
		8P + 16E	8P + 16E	?
High Perf Mobile		Arrow Lake HX	ARL-HX Refresh	Nova Lake HX
		8P + 16E	8P + 16E	?
Mainstream Mobile		Arrow Lake H	Panther Lake H
		6P + 8E	4P + 8E + 4LPe, N3E iGPU
Ultra Mobile		Lunar Lake - MX
		4P + 4E
Entry Ultra Mobile		Arrow Lake U	Panther Lake U
		2P + 6E	4P + 4LPe, Intel 3 iGPU
Low cost UM		Alder Lake N	Wildcat Lake
		8E	2P + 4LPe, Intel 18-A

 

[Magio]

Guys, I have compiled the upcoming Intel roadmap in the table below. Most of the information is known, so no surprise here. My source still could not tell me how many cores NVL going to have. Nor which process Intel going to use. Desktop version of NVL should launch in Q4 2026 with HX version launching in Q1 2027.

There is one document talk about PTL-MX but he is not sure can consider as LNL successor.

Again, this is Intel we are talking about, roadmap could change. I will update the table in case anything changes...

Year		2024 -25	2025 - 26	2026 - 27
Desktop		Arrow Lake S	ARL-S Refresh	Nova Lake S
		8P + 16E	8P + 16E	?
High Perf Mobile		Arrow Lake HX	ARL-HX Refresh	Nova Lake HX
		8P + 16E	8P + 16E	?
Mainstream Mobile		Arrow Lake H	Panther Lake H
		6P + 8E	4P + 8E + 4LPe, N3E iGPU
Ultra Mobile		Lunar Lake - MX
		4P + 4E
Entry Ultra Mobile		Arrow Lake U	Panther Lake U
		2P + 6E	4P + 4LPe, Intel 3 iGPU

What is that source? PTL-MX would be completely new info as far as I know, has that source gotten things right in the past?

 

[Ghostsonplanets]

Guys, I have compiled the upcoming Intel roadmap in the table below. Most of the information is known, so no surprise here. My source still could not tell me how many cores NVL going to have. Nor which process Intel going to use. Desktop version of NVL should launch in Q4 2026 with HX version launching in Q1 2027.

There is one document talk about PTL-MX but he is not sure can consider as LNL successor.

Again, this is Intel we are talking about, roadmap could change. I will update the table in case anything changes...

Year		2024 -25	2025 - 26	2026 - 27
Desktop		Arrow Lake S	ARL-S Refresh	Nova Lake S
		8P + 16E	8P + 16E	?
High Perf Mobile		Arrow Lake HX	ARL-HX Refresh	Nova Lake HX
		8P + 16E	8P + 16E	?
Mainstream Mobile		Arrow Lake H	Panther Lake H
		6P + 8E	4P + 8E + 4LPe, N3E iGPU
Ultra Mobile		Lunar Lake - MX
		4P + 4E
Entry Ultra Mobile		Arrow Lake U	Panther Lake U
		2P + 6E	4P + 4LPe, Intel 3 iGPU

Wildcat Lake should also be 25 - 26. Would be cool to have confirmation on the core count of it. Probably 2P + 4LPE + 2 Xe³ Celestial + 40 TOPs NPU.

What is that source? PTL-MX would be completely new info as far as I know, has that source gotten things right in the past?

People tracked some shipment data that showed a PTL SKU with on-package memory.

 

[Tigerick]

Wildcat Lake should also be 25 - 26. Would be cool to have confirmation on the core count of it. Probably 2P + 4LPE + 2 Xe³ Celestial + 40 TOPs NPU.

I checked with my source, some unique features of Wildcat Lake:

• Consists of two tiles with compute tile integrating CPU, GPU and NPU
• Compute tile will be fabbed by Intel 18-A
• PCD tile still on TSMC's N6.
• Mobile only and replacing ADL-N
• 2P + 4LPe with 2 XE3 GPU
• Single channel memory support
• First chiplet to use UCIe
• Expecting launching in Q2/Computex 2026

People tracked some shipment data that showed a PTL SKU with on-package memory.

 

[511]

I checked with my source, some unique features of Wildcat Lake:

• Consists of two tiles with compute tile integrating CPU, GPU and NPU
• Compute tile will be fabbed by Intel 18-A
• PCD tile still on TSMC's N6.
• Mobile only and replacing ADL-N
• 2P + 4LPe with 2 XE3 GPU
• Single channel memory support
• First chiplet to use UCIe
• Expecting launching in Q2/Computex 2026

They should go monolithic for these small dies their packing is costly

 

[Ghostsonplanets]

I checked with my source, some unique features of Wildcat Lake:

• Consists of two tiles with compute tile integrating CPU, GPU and NPU
• Compute tile will be fabbed by Intel 18-A
• PCD tile still on TSMC's N6.
• Mobile only and replacing ADL-N
• 2P + 4LPe with 2 XE3 GPU
• Single channel memory support
• First chiplet to use UCIe
• Expecting launching in Q2/Computex 2026

That's what I expected. Thanks for confirming it!

Although I wasn't expecting it single channel memory 😅. That will limit the effectiveness of the NPU.

They should go monolithic for these small dies their packing is costly

The idea is that all of Intel goes tiled going forward and allows them to reuse tiles, increase packaging volume and decrease costs , etc.

Monolithic dies are going to be very rare from Intel going forward. The fact Wildcat Lake, which is essentially Panther Lake U Lite for the budget market, is a tiled design shows that Intel has been able to bring advanced packaging to the budget market.

 

[511]

Monolithic dies are going to be very rare from Intel going forward. The fact Wildcat Lake, which is essentially Panther Lake U Lite for the budget market, is a tiled design shows that Intel has been able to bring advanced packaging to the budget market.

Looks like it but mono dies are still good for many use cases and considering wild lake spec I don't think it will go above 100mm2 combined only problem is the Die Hog NPU

 

[FlameTail]

Although I wasn't expecting it single channel memory 😅. That will limit the effectiveness of the NPU

Mobile SoCs such as the Snapdragon 8 Gen 3 have 45 TOPS NPUs, but with only "single channel memory".

 

[Ghostsonplanets]

Mobile SoCs such as the Snapdragon 8 Gen 3 have 45 TOPS NPUs, but with only "single channel memory".

Pretty sure they use 64-bit bus, which with LPDDR is akin to "dual-channel". Wildcat Lake will probably use LPDDR only. So I guess it's fine in that sense.

However, these premium mobile SoCs have loads of cache which I assume WCL will lack. So it remains to be seen. Given it's such a reduced core configuration, I guess it should be fine?

 

[Ghostsonplanets]

Bionic explained to me that WCL NPU (so far as far as he know) doesn't meet the 40 TOPs for Copilot +. Significantly cutdown from PTL U NPU.

So that make single-channel memory choice more acceptable. I

 

[511]

https://twitter.com/x/status/1822671710015131772

Apparently Next Forest is not canned