Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Thunder 57]

Intel quicksync ain't cpu based but dedicaded hardware decoder/encoder block.

Indeed, and it is good at what it does. But I have seen little info about it since SNB, I know it does h264, and I think h265. But AV1? Not so sure,

 

[coercitiv]

Indeed, and it is good at what it does. But I have seen little info about it since SNB, I know it does h264, and I think h265. But AV1? Not so sure,

I use Wikipedia to keep up with encoding/decoding from the usual suspects - Intel / Nvidia / AMD

Intel Quick Sync Video - Wikipedia

en.m.wikipedia.org

AV1 encoding is available in Arc GPUs, Meteor Lake and probably the upcoming ARL as well. I would assume Lunar Lake has it as well.

 

[511]

Meteor lake has Av1 encode and decode in QSV i have used it extensively

 

[SiliconFly]

Quicksync is gpu based,

Intel quicksync ain't cpu based but dedicaded hardware decoder/encoder block.

Intel QuickSync is a decicated hardware block that has nothing to do with the GPU. Starting MTL, it now resides in the SoC tile I think.

Quicksync is great, I loved it on my Ivy Bridge, It still resulted in a larger file size though. Whether that matters, well thats up to the user to decide,

QuickSync works very well in general. But there are some circumstances where some encoders can perform better without it, meaning better compression/quality at the cost of speed/efficiency.

I use Wikipedia to keep up with encoding/decoding from the usual suspects - Intel / Nvidia / AMD

Intel Quick Sync Video - Wikipedia

en.m.wikipedia.org

AV1 encoding is available in Arc GPUs, Meteor Lake and probably the upcoming ARL as well. I would assume Lunar Lake has it as well.

GPUs can definitely do a better job. But won't engaging the GPU might lead to loss in power efficiency?

Indeed, and it is good at what it does. But I have seen little info about it since SNB, I know it does h264, and I think h265. But AV1? Not so sure,

QuickSync is updated regularly gen-over-gen.

 

[mikk]

Shader assisted encoding from the GPU can be a little more flexible with somewhat better quality but wasn't big really and much much slower. Intel dropped GPU assisted encoding with Arc GPUs for this reason, it didn't make sense anymore. It's a fully fixed function encoding and quality improved at the same time. And nobody should use SB or IVB as a measure against hardware encoding because it hugely improved over the generations. Lunar Lake gets a new media engine, maybe it's even better there. Battlemage dGPU unfortunately doesn't get the new one from Lunar Lake.

 

[MS_AT]

Great post. Can you clarify this paragraph a bit more? Was the mistake that E cores didn't have AVX512 or that AVX512 was not correctly developed upon inception?

From E-cores point of view it would be better if AVX512 was introduced the same way that Intel plans to do with AVX10 now as that would make it more likely for them to implement them on the space constrained cores and wouldn't force them to drop AVX512 compatibility. But it is easy to say now, I guess no-one thought 7 years ago that Intel will need to do E-cores in mainstream on the inferior process.

Generally though I believe it would have been best if they handled it like AMD did with Granite/Strix. Mobile is still ISA compatible but has lower throughput. Skylake could have also been ISA compatible with Skylake-X but just double pump the execution units with smaller register files etc. This solution is better as you don't have to recompile your code. Just move the binary from Intel Core to Intel Xeon and enjoy the speed-up. But management wanted to make AVX512 a premium feature and now we see how it panned out. Not to mention they are slow learners as they wanted to sell licences to enable accelerators on Sapphire Rapids not so long ago, fortunately this idea went to the bin.

 

[naukkis]

Intel QuickSync is a decicated hardware block that has nothing to do with the GPU. Starting MTL, it now resides in the SoC tile I think.

Qs as other media cababilities are part of GPU media properties. MTL gpu is split design, shader and raster engine is in their own tile, rest of gpu including display controllers with media properties are placed on soc tile.

 

[LightningZ71]

Could Intel even feed AVX512 instruction streams on Arrow Lake if they had enabled it on both the P cores and the E cores? That's 24 cores all pushing very high throughput demands against 128 bits of DDR5. I suppose if they did 256 bit datapaths with double pumping, it wouldn't be too mismatched.

 

[gdansk]

Could Intel even feed AVX512 instruction streams on Arrow Lake if they had enabled it on both the P cores and the E cores? That's 24 cores all pushing very high throughput demands against 128 bits of DDR5. I suppose if they did 256 bit datapaths with double pumping, it wouldn't be too mismatched.

I would presume P cores would do full rate and e cores half rate. Effectively the same bandwidth requirement as 9950X. And unlike AMD it has a memory controller more equipped to feed it.

Of course it's all imaginary since Intel didn't go that route. But had they I think it'd be even better.

 

[MS_AT]

I would presume P cores would do full rate and e cores half rate. Effectively the same bandwidth requirement as 9950X. And unlike AMD it has a memory controller more equipped to feed it.

Of course it's all imaginary since Intel didn't go that route. But had they I think it'd be even better.

Even if it would be half rate on both, it would be a clear signal for software developers that it's worth to pay attention. Especially if the E-cores only CPUs would keep it, so it wouldn't be like Atoms of old, that were limited to SSE only for a very long time.

 

[SiliconFly]

Qs as other media cababilities are part of GPU media properties. MTL gpu is split design, shader and raster engine is in their own tile, rest of gpu including display controllers with media properties are placed on soc tile.

Yes. The Media Engine is in the SoC tile, but runs independently of the GPU tile. While running, it doesn't require the GPU tile to be powered on.

From AT:
"Starting things off, we have the Xe Media Engine, which is embedded within the SoC tile. Within the Xe Media Engine are two Multi-Format Codecs (MFX), designed and responsible for all the encoding and decoding tasks. Intel's Meteor Lake with Xe supports the latest codecs ranging from AV1 (decode and encode), HEVC, AVC, and VP9, with up to 8K60 HDR decode supported. For encoding, there's support for up to 8K resolutions with 10-bit color and HDR. Aiming to improve power efficiency on-chip with encode/decode workloads, having a dedicated Media Engine separate from the graphics allows Intel to find granular power savings as things are directed to the Xe Media Engine, which means the graphics tile doesn't need to be powered up to accomplish encode or decode tasks."

 

[mikk]

Yes. The Media Engine is in the SoC tile, but runs independently of the GPU tile. While running, it doesn't require the GPU tile to be powered on.

From AT:
"Starting things off, we have the Xe Media Engine, which is embedded within the SoC tile. Within the Xe Media Engine are two Multi-Format Codecs (MFX), designed and responsible for all the encoding and decoding tasks. Intel's Meteor Lake with Xe supports the latest codecs ranging from AV1 (decode and encode), HEVC, AVC, and VP9, with up to 8K60 HDR decode supported. For encoding, there's support for up to 8K resolutions with 10-bit color and HDR. Aiming to improve power efficiency on-chip with encode/decode workloads, having a dedicated Media Engine separate from the graphics allows Intel to find granular power savings as things are directed to the Xe Media Engine, which means the graphics tile doesn't need to be powered up to accomplish encode or decode tasks."

Prior to Arc graphics media engine had two modes, one was a hybrid of GPU+fixed function engine and the other a fully fixed function engine encoding mode (sometimes called low power mode). MTL or any Arc based graphics only support the full FF engine encoding mode which is much faster and power efficient.

https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2024-1/media-engine.html

 

[LightningZ71]

I would presume P cores would do full rate and e cores half rate. Effectively the same bandwidth requirement as 9950X. And unlike AMD it has a memory controller more equipped to feed it.

Of course it's all imaginary since Intel didn't go that route. But had they I think it'd be even better.

Since Intel has a history of having consumer cores and xeon cores differing on AVX512, it's not far fetched to see the P cores being either half OR full rate on consumer dies. To keep die sizes manageable, and offer differentiation with xeon dies, it would make sense for consumer died as half rate.

 

[DavidC1]

Generally though I believe it would have been best if they handled it like AMD did with Granite/Strix. Mobile is still ISA compatible but has lower throughput. Skylake could have also been ISA compatible with Skylake-X but just double pump the execution units with smaller register files etc.

The extra registers even doing 256-bit mode still costs quite a bit of more transistors apparently.

Since it was a misguided idea in the first place, there can't be a clean way of resolving the issue.

 

[OneEng2]

So I have a couple of questions on the up-coming Intel CPU releases.....

One, I originally heard that Intel would be making the CPU tile on their own 20A Intel process. Most recently, I hear they are moving that to TSMC .... which I am guessing would be their N3E or N3P. I am not clear on the proposed density improvements of N3P over N3E, but my guess is it isn't drastic (say 5%).

Lets say that Arrow Lake is being produced on N3E. It looks like Arrow lake is 4% faster single core and 14% faster in multi-core than AMD's 9550 (according to the latest leaks I can find).

So, sounds good but .....

Arrow lake is boasting a 24 core processor against a 16 core processor. Sure, ZEN5 has hyper-threading, but I believe the last time I did some numbers, it is really only good for about 20% (in multi-threaded apps).

So all things being equal, an AMD Zen 5 core is worth 1.2 Arrow Lake cores ... or 19 cores.

So overall, Arrow lake utilizing a process node allowing 1.5x the number of transistors of Zen 5 is getting14% higher multi-core performance using a node that is considerably more expensive (N3E I think) than Zen 5 (N4P).

I have a feeling that AMD's memory controller and IO for consumer are likely limited to 16 cores at this time. Otherwise, 2 more cores would bring a Zen 5 up to par with the Arrow Lake.

A die shrink for AMD to N3E seems like it would more than put the next AMD processor ahead on all fronts.

So will Intel still be beading red after Arrow Lake? Will AMD just lower prices on their less expensive processor and force Intel to give up profit?

I am also not sure about energy efficiency, but I am excited to see the detailed reviews on Arrow Lake when they come out. This will be the first time EVER that we will be able to compare Intel and AMD designs on an equal process node (when AMD makes the shrink to N3E).

I have been following processor design between AMD and Intel for decades. I have always thought that Intel's biggest advantage was the fact that they always had 1.5 to 2 times the transistor budget as AMD at any given point in history.

It is now starting to look like that advantage will be erased. Interesting times.

 

[Josh128]

So I have a couple of questions on the up-coming Intel CPU releases.....

One, I originally heard that Intel would be making the CPU tile on their own 20A Intel process. Most recently, I hear they are moving that to TSMC .... which I am guessing would be their N3E or N3P. I am not clear on the proposed density improvements of N3P over N3E, but my guess is it isn't drastic (say 5%).

Lets say that Arrow Lake is being produced on N3E. It looks like Arrow lake is 4% faster single core and 14% faster in multi-core than AMD's 9550 (according to the latest leaks I can find).

So, sounds good but .....

Arrow lake is boasting a 24 core processor against a 16 core processor. Sure, ZEN5 has hyper-threading, but I believe the last time I did some numbers, it is really only good for about 20% (in multi-threaded apps).

So all things being equal, an AMD Zen 5 core is worth 1.2 Arrow Lake cores ... or 19 cores.

So overall, Arrow lake utilizing a process node allowing 1.5x the number of transistors of Zen 5 is getting14% higher multi-core performance using a node that is considerably more expensive (N3E I think) than Zen 5 (N4P).

I have a feeling that AMD's memory controller and IO for consumer are likely limited to 16 cores at this time. Otherwise, 2 more cores would bring a Zen 5 up to par with the Arrow Lake.

A die shrink for AMD to N3E seems like it would more than put the next AMD processor ahead on all fronts.

So will Intel still be beading red after Arrow Lake? Will AMD just lower prices on their less expensive processor and force Intel to give up profit?

I am also not sure about energy efficiency, but I am excited to see the detailed reviews on Arrow Lake when they come out. This will be the first time EVER that we will be able to compare Intel and AMD designs on an equal process node (when AMD makes the shrink to N3E).

I have been following processor design between AMD and Intel for decades. I have always thought that Intel's biggest advantage was the fact that they always had 1.5 to 2 times the transistor budget as AMD at any given point in history.

It is now starting to look like that advantage will be erased. Interesting times.

Lunar Lake is on N3B. Arrow Lake is likely on a higher performance variant of N3. Lunar Lake should make much more money for Intel than Arrow Lake, being that its going into premium laptops that command higher margins and is a lot less silicon area than Arrow Lake.

Arrow Lake will likely be expensive, so I have my doubts AMD will lower Zen 5 desktop prices due to Arrow Lake. Zen 5 desktop is AMDs second least profitable business, only consumer /desktop GPU is less profitable. They would rather sell the silicon in EPYC, Instinct/MI, or laptop at higher prices than sell desktop at lower prices.

 

[Ghostsonplanets]

N3E or N3P

Everything is N3B. In the final stage before being cancelled, the 20A tile was a small volume 6+8. ARL + LNL generation was always planned to be manufactured on TSMC N3 process.

 

[511]

Outside of I3 they are still at Intel iirc

 

[Henry swagger]

https://videocardz.com/newz/intel-developing-cobra-core-architecture-on-x86-potential-successor-to-royal-core

cobra core follows after royal core.. 🤔😃

 

[del42sa]

https://videocardz.com/newz/intel-developing-cobra-core-architecture-on-x86-potential-successor-to-royal-core

cobra core follows after royal core.. 🤔😃

Royal Core is MLID propaganda such as Rentable Units pacifier

so next one is Cobra Core with Naja Units

 

[SiliconFly]

https://videocardz.com/newz/intel-developing-cobra-core-architecture-on-x86-potential-successor-to-royal-core

cobra core follows after royal core.. 🤔😃

Cobra Core??? Really? What the hell is it?

SOUNDS REAL AWESOME!

But one thing is very clear. Intel indeed used the name Royal Core for one of its projects. So, the Royal Core name actually is very real.

 

[511]

Leaked Excel Sheet from the file looks Interesting Cougar Cove and Panther Cove for Noval lake iirc Cougar is 5-10% IPC Increase while Panther is double digit over Cougar
[ Not a leaked roadmap]

 

[SteinFG]

This is not a roadmap, I'm 90% sure it's just an excel sheet someone ouside of intel did

 

[cebri1]

This is not a roadmap, I'm 90% sure it's just an excel sheet someone ouside of intel did

This. And it’s wrong, there is no PTL-S.

 

[511]

Oh yes needs to be updated anyway this was from the link