Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[OneEng2]

It was derisking. The more interesting point for me is that the goals of 18a are much more watered down than they were a while ago. 18a has benefits much more in like with what 20a was supposed to offer Vs intel 3.

Can you elaborate on the original vs current 18A plans? AFAIK 18A is still going to have BSPD and GAA?

 

[OneEng2]

A new aside...

What the crap is going on with process naming these days?

When we were in the micrometer range, it was a pretty good gauge of the relative "goodness" of a process and you could mostly determine the transistor density differences between processes.

Now, I am more reminded of the P4 days when suddenly a 2.6Ghz processor got beaten by a 2.0Ghz processor from another family of chips (it may have actually been worse than this. It was some time ago ). As a result, AMD started naming their chip "model number" a number that appeared like a clock frequency .... and the clock frequency naming convention was permanently lost.

It feels very much the same now with process nodes. Ah well, can't very well do anything about it. Just have to get used to the idea I guess.

So how does 18A compare to TSMC's N3E and N3P. The reason I ask (in this thread) is because of the possibility that Intel will again punt on a process (this time 18A) and drop back to a TSMC production facility to bail out a CPU program.

Looks like TSMC isn't offering anything big in process changes until 16A in H2 2026 so largely speaking, AMD will be left with about the same transistor density and power limits until then (within about 15%). If Intel 18A is indeed not even a match in transistor density and power limits to TSMC's N3X (not to mention N2 which is slightly better in H2 2024), it doesn't seem like there is much room in the server processor space for wild growth beyond what is already planned for 2025 until around 2027.

And again, my curiosity is how Intel fares against AMD when forced to compete on an equal process node. Suddenly, the CPU architecture designs will be the most important part of the equation as the process will not be able to give Intel its traditional advantages in power and transistor count on the same die size as it has in the past.

I actually think this will make for much more interesting discussions as there are LOTS more variables to consider in how well an architecture performs as there are to how well a process performs ..... and architectural tweaks can be made much more quickly these days as process changes stretch out forever.

 

[9949asd]

This is not 17W PL1, score too high. Maybe 30W PL1 with 37W PL2.

only 288v is 30w pl1.

 

[Wolverine2349]

A new aside...

What the crap is going on with process naming these days?

When we were in the micrometer range, it was a pretty good gauge of the relative "goodness" of a process and you could mostly determine the transistor density differences between processes.

Now, I am more reminded of the P4 days when suddenly a 2.6Ghz processor got beaten by a 2.0Ghz processor from another family of chips (it may have actually been worse than this. It was some time ago ). As a result, AMD started naming their chip "model number" a number that appeared like a clock frequency .... and the clock frequency naming convention was permanently lost.

It feels very much the same now with process nodes. Ah well, can't very well do anything about it. Just have to get used to the idea I guess.

So how does 18A compare to TSMC's N3E and N3P. The reason I ask (in this thread) is because of the possibility that Intel will again punt on a process (this time 18A) and drop back to a TSMC production facility to bail out a CPU program.

Looks like TSMC isn't offering anything big in process changes until 16A in H2 2026 so largely speaking, AMD will be left with about the same transistor density and power limits until then (within about 15%). If Intel 18A is indeed not even a match in transistor density and power limits to TSMC's N3X (not to mention N2 which is slightly better in H2 2024), it doesn't seem like there is much room in the server processor space for wild growth beyond what is already planned for 2025 until around 2027.

And again, my curiosity is how Intel fares against AMD when forced to compete on an equal process node. Suddenly, the CPU architecture designs will be the most important part of the equation as the process will not be able to give Intel its traditional advantages in power and transistor count on the same die size as it has in the past.

I actually think this will make for much more interesting discussions as there are LOTS more variables to consider in how well an architecture performs as there are to how well a process performs ..... and architectural tweaks can be made much more quickly these days as process changes stretch out forever.

Intel still has the better processor design. I mean even on inferior 10nm Inel own node, Golden Cove spanked Zen 3 in IPC and clocks. Even at par with Zen 4 in IPC or slightly ahead./

AMD just 8 core CCXs and no more cores per CCX even on HEDT Threadripper and EPYC Intel on Workstation and Server space can get more than 8 big cores on a single mesh or tile unlike AMD. Intel can do up to 12 P core or 16 e-core on current design as 4 e-cores take space of one P core.

And with rapid insane improvement of Skymont e-cores to have Raptor Cove IPC the Skymont cores already have IPC (6-9%) ahead of Zen 4 though a 500-900MHz clock speed deficiency compared to Zen 4 and 5. But Lion Cove has a 15% IPC uplift over Raptor Cove and can match or exceed Zen 4 and 5 clocks.

Intel has better CPU design.

Issue is can Intel just let it go with there Foundries. They are having trouble with their foundries and its just not working no producing good reliable yields on 10nm and beyond except maybe Alder Lake and a few mobile things before ALD? They need to just let it go and be like Apple and NVIDIA and AMD and let TSMC and oithers do it all for them whiule they design CPUs.

AMD is not going much of anywhere especially in mobile space with Intel Lunar Lake spanking it and beyond 8 cores in desktop space except for a VM hosting machine or non latency sensitive productivity forget about it with their max of 8 core CCX/CCDs which appears to not be changing ever.

 

[mikk]

only 288v is 30w pl1.

No any Lunar Lake can use PL1 up to 37W. 17W is just a base PL1. PL2 can be configured as PL1 if OEMs wants. And PL2 is up to 37W on any Lunar Lake SKU.

 

[fastandfurious6]

Intel has better CPU design.

Corroding CPUs is a classic landmark of stellar CPU design!

 

[Wolverine2349]

Corroding CPUs is a classic landmark of stellar CPU design!

The Raptopr Lake design was a trianwreck. Stability nightmare. But the ring bus and core to core to core latency beyond 8 cores is superior. Alder Lake was pretty good They just need better foundries to make them.

Their foundries are a mess.

What does AMD have? They cannot go beyond 8 cores on a single CCX. Their infinity fabric is limiting. though yes AMD currnet offering is so much better than Intel's because it does not corrode. But once Arrow Lake comes out, that likely changes.

 

[9949asd]

No any Lunar Lake can use PL1 up to 37W. 17W is just a base PL1. PL2 can be configured as PL1 if OEMs wants. And PL2 is up to 37W on any Lunar Lake SKU.

What are you talking about, pl1 17w ,pl2 30w 26s, the max power limit is 37w. Only the 288v can be 30w all time.

 

[SiliconFly]

Corroding CPUs is a classic landmark of stellar CPU design!

And Zen 5% is the hallmark of stellar CPU design!

Kudos to their design team. After 2 years of development, they have only 5% to show for it.

The Raptopr Lake design was a trianwreck. Stability nightmare. But the ring bus and core to core to core latency beyond 8 cores is superior. Alder Lake was pretty good They just need better foundries to make them.

Their foundries are a mess.

What does AMD have? They cannot go beyond 8 cores on a single CCX. Their infinity fabric is limiting. though yes AMD currnet offering is so much better than Intel's because it does not corrode. But once Arrow Lake comes out, that likely changes.

Very true. Their foundries are a mess. But they're not dependent on their foundries anymore. Most are outsourced. And with the kinda silicon volume Intel handles, they'll always have access to better TSMC nodes compared to AMD.

AMD's node advantage is history. AMD's radical designs are history. AMD now has to be content being runner up.

 

[mikk]

What are you talking about, pl1 17w ,pl2 30w 26s, the max power limit is 37w. Only the 288v can be 30w all time.

PL2 can be configured as PL1, it was always like this. There is no hard PL1 limit on Intel CPUs, it just can't go beyond PL2.

 

[Det0x]

but doesn't he know?? real men have fabs

Intel splits off foundry business — new dawn for chip giant as it announces major transformation plans

Intel Foundry Service will get more financial transparency and flexibility

www.techradar.com

*edit*
Wrong thread

 

[alcoholbob]

The Raptopr Lake design was a trianwreck. Stability nightmare. But the ring bus and core to core to core latency beyond 8 cores is superior. Alder Lake was pretty good They just need better foundries to make them.

Their foundries are a mess.

What does AMD have? They cannot go beyond 8 cores on a single CCX. Their infinity fabric is limiting. though yes AMD currnet offering is so much better than Intel's because it does not corrode. But once Arrow Lake comes out, that likely changes.

Supposedly the Raptor Lake ringbus was never really designed to deal with 16 E-Cores, and that's why there's a segregated voltage rail in Arrow Lake for the e-cores. We'll see how well ARL is faring after giving it some months after launch I suppose.

With AMD they absolutely can go beyond 8 cores per CCX, they just have no interest in offering anything but the cheapest scraps of server reject chips to consumers so they can maximize their margins. Even Zen 4 server CPUs had configurations with 16 core CCDs, and so will Zen 5 server parts. This is entirely a function of AMD milking the consumer.

 

[Thunder 57]

AMD's node advantage is history. AMD's radical designs are history. AMD now has to be content being runner up.

Bold prediction. Maybe wait until we see how ARL turns out?

 

[Hitman928]

Supposedly the Raptor Lake ringbus was never really designed to deal with 16 E-Cores, and that's why there's a segregated voltage rail in Arrow Lake for the e-cores. We'll see how well ARL is faring after giving it some months after launch I suppose.

With AMD they absolutely can go beyond 8 cores per CCX, they just have no interest in offering anything but the cheapest scraps of server reject chips to consumers so they can maximize their margins. Even Zen 4 server CPUs had configurations with 16 core CCDs, and so will Zen 5 server parts. This is entirely a function of AMD milking the consumer.

Those 16 core CCDs were Zen 5c cores.

 

[9949asd]

PL2 can be configured as PL1, it was always like this. There is no hard PL1 limit on Intel CPUs, it just can't go beyond PL2.

Lunar lake is ultra thin notebook chip, PL2=PL1? What are you talking about? This is not desktop.

 

[Tigerick]

Please look at the specs of LNL in the front page. PL2 is always set at 37W, PL1 could be set to 8W, 17W or 30W depends on OEMs and cooling solution.

 

[inquiss]

Can you elaborate on the original vs current 18A plans? AFAIK 18A is still going to have BSPD and GAA?

The performance and density targets for 18a have changed. Compare what intel used to say for 18a over 20a and 20a over 3, so two shrinks to what it is now saying 18a will be over 3 and the improvements that 18a should have had are now much less, closer to what they used to say 20a was over 3

 

[DavidC1]

The Lenovo Yoga is tested with 1080p resolution by the way, which most current Lunarlake devices won't ship with.

Most will be using a 1440p or even higher OLED display and be a power hog, eliminating most of the advantages the platform has.

Lunar lake is ultra thin notebook chip, PL2=PL1? What are you talking about? This is not desktop.

There's not necessarily a set PL1 TDP on laptops. It is pretty loose. My Yoga is 5W PL1, but it goes up to 7W PL1 on more demanding scenarios. And it would change depending on Tablet Mode and Clamshell Mode.

Unlike what the spec sheet says, anywhere between 17W and 30W is likely up for use by the manufacturer.

It may be confusing, but having it fixed isn't really an advantage, because it limits what kind of devices and cooling and form factors it can be used in.

 

[9949asd]

The Lenovo Yoga is tested with 1080p resolution by the way, which most current Lunarlake devices won't ship with.

Most will be using a 1440p or even higher OLED display and be a power hog, eliminating most of the advantages the platform has.

There's not necessarily a set PL1 TDP on laptops. It is pretty loose. My Yoga is 5W PL1, but it goes up to 7W PL1 on more demanding scenarios. And it would change depending on Tablet Mode and Clamshell Mode.

Unlike what the spec sheet says, anywhere between 17W and 30W is likely up for use by the manufacturer.

It may be confusing, but having it fixed isn't really an advantage, because it limits what kind of devices and cooling and form factors it can be used in.

Of course pl1 is not always 17w, it’s means the limit is 17w, the real power consumption depends on the task.

 

[SiliconFly]

The performance and density targets for 18a have changed. Compare what intel used to say for 18a over 20a and 20a over 3, so two shrinks to what it is now saying 18a will be over 3 and the improvements that 18a should have had are now much less, closer to what they used to say 20a was over 3

It’s not possible to change PPA once PDKs are in place. That too this late in the cycle.

Foundry customers can’t just ditch the existing PDKs and switch to a new one just cos the foundry decided to suddenly the change ita mind.

 

[Wolverine2349]

Those 16 core CCDs were Zen 5c cores.

Yes exactly. AMD has no more than 8 normal strong cores on a single CCX/CCD.

And same with Zen 6 it appears.

Only 16 Zen 6C cores on a CCX. They may have 32 even weaker c cores on a CCD per rumors. But only 8 Big cores on a CCX.

And still 8 normally cores per CCX and the stupid severe cross CCX/CCD latency penalty.

AMND has very good 8 core parts since Zen 3, but they really need to get more than 8 big cores on a CCX. Intel has a better design in that regard as they have way more than 8 big cores on a single tile or mesh with their high end server and enterprise Saphire rapids and beyond.

 

[poke01]

The Lenovo Yoga is tested with 1080p resolution by the way, which most current Lunarlake devices won't ship with.

If that’s the case that battery life test is less meaningful, because the Air 15” has a 1664p resolution.

So using a 1200p resolution on the yoga is what you expect from first party tests..

 

[Hitman928]

It’s not possible to change PPA once PDKs are in place. That too this late in the cycle.

Foundry customers can’t just ditch the existing PDKs and switch to a new one just cos the foundry decided to suddenly the change ita mind.

Lots of things can change until you get to the release/production PDK.

 

[511]

It’s not possible to change PPA once PDKs are in place. That too this late in the cycle.

Foundry customers can’t just ditch the existing PDKs and switch to a new one just cos the foundry decided to suddenly the change ita mind.

Well you can TSMC does this you can simply upgrade design from say N5 -> N4 iirc without much trouble

 

[511]

If that’s the case that battery life test is less meaningful, because the Air 15” has a 1664p resolution.

So using a 1200p resolution on the yoga is what you expect from first party tests..

Yes but we forgot the refresh rate it is 1200P 120hz vs 60hz on air there is that as well