Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[A///]

Is that English?

 

[mikk]

I literarily just proved it.

No you don't and you cannot. There is no source from Intel where they confirmed 18A is using High-NA, it's the opposite. Also H2 2024 manufacturing ready doesn't match with the readiness of High-NA. This is how wrong speculations emerge by the way.

 

[Geddagod]

No you don't and you cannot. There is no source from Intel where they confirmed 18A is using High-NA, it's the opposite. Also H2 2024 manufacturing ready doesn't match with the readiness of High-NA. This is how wrong speculations emerge by the way.

H2 2024 manufacturing ready. Intel 18A is launching in 2025 for Clear Water forest, and will ramp throughout the year. Do you think Intel 16A will be in HVM in 2025 then?

 

[Geddagod]

Is that English?

What? Ye C&C server is english... chips and cheese? You know the website that does niche reviews?

 

[msj10]

Meteor Lake will have an L4 cache die?

LLC をサポートせず、ADM/L4キャッシュをサポートする Meteor Lake GPU | Coelacanth's Dream

Intel の Fei Yang 氏より、intel-gfx メーリングリストに公開されたパッチにて Meteor Lake GPU では LLC (Last Level Cache) をサポートせず、新たに ADM/L4キャッシュをサポートすることが明かさ

www.coelacanth-dream.com

 

[igor_kavinski]

Knew Intel would pull something like that to counter the latency increase from shifting the IMC onto the I/O die.

 

[Hulk]

Meteor Lake will have an L4 cache die?

LLC をサポートせず、ADM/L4キャッシュをサポートする Meteor Lake GPU | Coelacanth's Dream

Intel の Fei Yang 氏より、intel-gfx メーリングリストに公開されたパッチにて Meteor Lake GPU では LLC (Last Level Cache) をサポートせず、新たに ADM/L4キャッシュをサポートすることが明かさ

www.coelacanth-dream.com

At first glance this looks like a return to "Crystal Well" to support the rumored increased iGPU performance of Meteor Lake.

But there is probably more to it as Intel it seems has been trying to optimize cache structure as core counts increase and they move to a tiled format. Will they continue to go with a shared L3 like SPR for all cores or will they eventually move to L3 desegrated to clusters of cores aka AMD Zen? We know that there is quite a latency penalty when Golden Cove reaches for L3 and that's probably why it was important to increase L2 in Raptor Cove in order to mitigate that effect.

 

[deasd]

Bad sign. 14th gen (RPL-Refresh and MTL)seems to be a longer peroid product than previous speculation, it include RPL-S, HX, and MTL which are low power SKUs only. This would be another 'Coffeelake+Cannonlake' situation until full-lineup Arrowlake arrive.

https://twitter.com/x/status/1645654155028221952

 

[Exist50]

Bad sign. 14th gen (RPL-Refresh and MTL)seems to be a longer peroid product than previous speculation, it include RPL-S, HX, and MTL which are low power SKUs only. This would be another 'Coffeelake+Cannonlake' situation until full-lineup Arrowlake arrive.

https://twitter.com/x/status/1645654155028221952

The HX line has used desktop silicon since Day 1. Not really a surprise.

 

[igor_kavinski]

Kinda makes sense. Intel will learn and improve yields on Intel 4 with MTL and when it's in good shape frequencywise, they will release ARL on Intel 4/3.

 

[A///]

Although cache latency has been discussed there will also be a penalty somewhere in the process, how much of which lies on the strength and weaknesses of whatever inter connect Intel has developed for this "glue" going forward.

 

[A///]

Kinda makes sense. Intel will learn and improve yields on Intel 4 with MTL and when it's in good shape frequencywise, they will release ARL on Intel 4/3.

Correct, It's not unusual... to be loved by anyone... because Intel and other companies are known to throw sacrificial lambs to the silicon spirits to get things right. Meteor lake will all but be forgotten in years time.

 

[Geddagod]

Kinda makes sense. Intel will learn and improve yields on Intel 4 with MTL and when it's in good shape frequencywise, they will release ARL on Intel 4/3.

First time I'm hearing any rumor that ARL will be on Intel 4 or Intel 3...

 

[Geddagod]

Although cache latency has been discussed there will also be a penalty somewhere in the process, how much of which lies on the strength and weaknesses of whatever inter connect Intel has developed for this "glue" going forward.

For the L1, L2, and L3 it really shouldn't matter since they ae all contained to one compute tile, no? I'm guessing the only large impact would be on memory latency, but I also suspect L3 cache latency could be lowered with MTL...

 

[Geddagod]

Knew Intel would pull something like that to counter the latency increase from shifting the IMC onto the I/O die.

I think it's a little funny that Intel would include the IMC on the compute tile on their server CPUs, even on Granite Rapids where it has a separate IO tile, but on client it's not. Very curious how latency is going to be effected, maybe the impact is not too bad? Odd design choice otherwise IMO

 

[Geddagod]

At first glance this looks like a return to "Crystal Well" to support the rumored increased iGPU performance of Meteor Lake.

But there is probably more to it as Intel it seems has been trying to optimize cache structure as core counts increase and they move to a tiled format. Will they continue to go with a shared L3 like SPR for all cores or will they eventually move to L3 desegrated to clusters of cores aka AMD Zen? We know that there is quite a latency penalty when Golden Cove reaches for L3 and that's probably why it was important to increase L2 in Raptor Cove in order to mitigate that effect.

Ehhhh this was rumored a couple months ago. This is more evidence, but honestly, if there is an L4, I'm very cautious in believing it's going to be on the base tile, unlike my position on this when this rumor first emerged due to some code spotted that referenced it IIRC.
About changing cache structuring, EMR is not likely to change the cache structure like that IMO because it reduces number of tiles to two to improve latency, and GNR too, all that effort into including IMCs into the compute tiles and low number of compute tiles makes it seem like Intel wants to continue the massive shared L3 strategy.
I'm guessing the earliest this change might occur is DMR based on the mockup we saw and how it looks to be organized very much like AMD organizes their CPUs, if it ever changes.
Also I think their L3 cache weaknesses aren't going to be fixed by making the cache private to each chiplet like AMD does though. They still run their mesh clocks lower than their core clock IIRC, and also they still have to connect way more cores in a single chiplet anyway, so they still have to use mesh.

 

[Geddagod]

The HX line has used desktop silicon since Day 1. Not really a surprise.

Intel should have made the 11900HX use rocket lake instead of tiger lake

 

[Geddagod]

Correct, It's not unusual... to be loved by anyone... because Intel and other companies are known to throw sacrificial lambs to the silicon spirits to get things right. Meteor lake will all but be forgotten in years time.

Eh, MTL is going to be the first product to look at Intel's ability to turn things around execution wise.
From a technical perspective, it's going to be extremely interesting too. Low power cores on SOC tile, Tiled architecture, all the works haha
From a product perspective, the low power cores on the SOC tile might be impressive for idle and web surfing battery life. And MT core performance might not be much, but the iGPU performance is another story completely.
I'm curious though, if MTL ends up being able to hit the rumored ~5.5GHz, and launches to desktop (even as a 6+8), how much worse is it going to be versus RPL in gaming really? Less L3 because of lack of E-cores adding on extra L3, but latency could be better on that L3 even barring just having less of it because less stops on the ring. Potential for L4, and a better L4 than what Intel did in the past, which has been shown to help gaming performance by 15% on broadwell, though how that will translate to MTL is less sure. And then there is presumably going to be a regression with memory latency, but MTL should also support higher frequency DDR5 than Intel does with RPL. RWC should have some small IPC improvements, but max ST clocks would also be like 4% worse than RPL too, and of course, only being 6 cores vs 8 cores for P-cores.

 

[igor_kavinski]

First time I'm hearing any rumor that ARL will be on Intel 4 or Intel 3...

I know that the roadmap shared by Intel states that ARL is slated to use 20A but considering that Intel can't even get Intel 4 at the point they want it to be and had to resort to RPL refresh to buy some extra time, I think it is very optimistic to assume they might get 20A working at the same time as Intel 4. However, this is me speculating with no idea what's special about 20A. Maybe Intel 4 is tuned for power efficiency while 20A is optimized for maximum frequency and both are just similar processes with different materials to meet their desired goals?

 

[igor_kavinski]

Odd design choice otherwise IMO

Maybe decoupling the IMC from the compute tile has some advantages like higher possible frequencies? Or maybe the IMC generates enough heat that it's a detriment to the compute transistors?

 

[Geddagod]

I know that the roadmap shared by Intel states that ARL is slated to use 20A but considering that Intel can't even get Intel 4 at the point they want it to be and had to resort to RPL refresh to buy some extra time, I think it is very optimistic to assume they might get 20A working at the same time as Intel 4. However, this is me speculating with no idea what's special about 20A. Maybe Intel 4 is tuned for power efficiency while 20A is optimized for maximum frequency and both are just similar processes with different materials to meet their desired goals?

TSMC 3nm is what rumors have been saying.
Intel 20A would be working at the same time as Intel 3 would be working (For GNR/SRF) but I get your point.
Who knows maybe it will be Intel 3 : )

 

[A///]

For the L1, L2, and L3 it really shouldn't matter since they ae all contained to one compute tile, no? I'm guessing the only large impact would be on memory latency, but I also suspect L3 cache latency could be lowered with MTL...

as I pointed out yes? the issue is how many compute tiles there will be going forward for Intel. If there's more than one there will be inter tile latency. If a single compute tile + cache exist the latency with other ip would be so little it wouldn't matter. That post was a continuation of what I said a few days ago to someone else talking about raptor refresh. there's no one prominent design that's the best of all time as you know but certain applications of methods will garner a higher performing product, you take and you give a little.

will intel use multiple compute dies in client products? who knows it's not on any roadmap right now. could intel change things? sure, it wouldn't be a new phenomena from intel. my personal opinion which means nothing is intel may have trouble getting avx512 and mt working on e cores and drop them in favor for compute dies with more cores. this or even some of the wild theories people have about their main competitor who I shan't name because of the mods, is it's not very realistic. board space is a premium right now and the larger a package the more difficult it may be to get it to install correctly. You can refer to what I said earlier in this post, you take a nd you ve give a little. you can't keep taking with no risk to the product. You gotta realise that most of what we discuss on this forum or any online community isn't often set in stone and if either company makes a breakthrough in their labs will we'll likely see that implemented instead of what was trumbling around the rumor mills. that suggestion is far fetched but i don't like to rule anything out in life.

 

[A///]

Eh, MTL is going to be the first product to look at Intel's ability to turn things around execution wise.
From a technical perspective, it's going to be extremely interesting too. Low power cores on SOC tile, Tiled architecture, all the works haha
From a product perspective, the low power cores on the SOC tile might be impressive for idle and web surfing battery life. And MT core performance might not be much, but the iGPU performance is another story completely.
I'm curious though, if MTL ends up being able to hit the rumored ~5.5GHz, and launches to desktop (even as a 6+8), how much worse is it going to be versus RPL in gaming really? Less L3 because of lack of E-cores adding on extra L3, but latency could be better on that L3 even barring just having less of it because less stops on the ring. Potential for L4, and a better L4 than what Intel did in the past, which has been shown to help gaming performance by 15% on broadwell, though how that will translate to MTL is less sure. And then there is presumably going to be a regression with memory latency, but MTL should also support higher frequency DDR5 than Intel does with RPL. RWC should have some small IPC improvements, but max ST clocks would also be like 4% worse than RPL too, and of course, only being 6 cores vs 8 cores for P-cores.

A cleaner gen establishes a new process or set of features and you still deliver a viable product but how good it is depends on various factors but there's a handful of intel released I would consider a cleaner generation. I wouldn't consider Raptor a cleaner generation, it's built on what was learned from alder gen. You are right here with meteor going a new direction but arrow is on a newer process and that process is untested. In the older days you couldn't sit out for a few years when your hw would get blown away by something coming down the line in 7 months for example. my opinons today as an old timer may not mesh with more youthful users but throwing caution to the wind on a new design practice like meteor or a few years ago with alder, or a very new untested in scale process like for arrow is a risk I personally don't want to take. and given today's performance leaps you want a nice wide performance gap to exist to make your spending your hard earned money reasonable.

now if intel succeeds with their tech stack for their processes and it signifcantly improves processors in everything within reason and their yield rates which is about as likely as aliens visiting us and smoking an abnormally thick spliff with a ressurected Jesus, then ifs orders will climb and tsmc will have some competition on their hands they didn't quite expect because I do feel they've written off intel as a competitor now. if samsung can stop getting high on paint can vapours and get their own gaafet in order then it would add variety to the market of those who seek third party fabbing which would be niche hardware companies operating at low orders but need cutting edge nodes or any fabless company that makes a lot of hardware. tsmc will need to adjust prices. a win for all the companies but we consumers get the short end of the stick, none of those savings get passed onto us.

 

[Geddagod]

as I pointed out yes? the issue is how many compute tiles there will be going forward for Intel. If there's more than one there will be inter tile latency. If a single compute tile + cache exist the latency with other ip would be so little it wouldn't matter. That post was a continuation of what I said a few days ago to someone else talking about raptor refresh. there's no one prominent design that's the best of all time as you know but certain applications of methods will garner a higher performing product, you take and you give a little.

will intel use multiple compute dies in client products? who knows it's not on any roadmap right now. could intel change things? sure, it wouldn't be a new phenomena from intel. my personal opinion which means nothing is intel may have trouble getting avx512 and mt working on e cores and drop them in favor for compute dies with more cores. this or even some of the wild theories people have about their main competitor who I shan't name because of the mods, is it's not very realistic. board space is a premium right now and the larger a package the more difficult it may be to get it to install correctly. You can refer to what I said earlier in this post, you take a nd you ve give a little. you can't keep taking with no risk to the product. You gotta realise that most of what we discuss on this forum or any online community isn't often set in stone and if either company makes a breakthrough in their labs will we'll likely see that implemented instead of what was trumbling around the rumor mills. that suggestion is far fetched but i don't like to rule anything out in life.

I just don't think it makes much sense. At least for ARL and MTL.

 

[A///]

I just don't think it makes much sense. At least for ARL and MTL.

what intel is doing?