Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[uzzi38]

Or maybe it is simply because their cpus run hot and use too much power already. Naw, that would be too simple. Much better to infer some malicious motive. Lots of projection in this post, young Padawan.

AVX-512 was not the thing that was going to push it over the edge, especially not when you had to disable all the e-cores in order to use it.

Those e-cores aren't exactly free for power usage.

Besides, Intel's client implementation of AVX-512 is also 2x256b afaik, and we saw on ICL and TGL that it didn't have that significant of an impact on power. It's just a shame the option is gone. The malicious motives are unnecessary and I agree with you on that point, but the overall complaint of AVX-512 being removed I think is still valid.

 

[igor_kavinski]

I can see why your mind is going to that because of the naming rumor article from a few days ago.

Hadn't seen that rumor but it seems to confirm that Intel is VERY predictable. They don't want to explain to investors, I guess, about why a year later they are releasing 13th gen refresh parts so they just call them 14th gen and pretend that they made a gen worth of progress.

 

[Hulk]

View attachment 79480

Hadn't seen that rumor but it seems to confirm that Intel is VERY predictable. They don't want to explain to investors, I guess, about why a year later they are releasing 13th gen refresh parts so they just call them 14th gen and pretend that they made a gen worth of progress.

Raptor Lake Refresh

Past history shows Intel to have progressed from one generation to the next using at least one of the following.

1. New architecture - Lots of examples of this but we can look at Comet Lake to Rocket Lake as an example of keeping the same node and advancing architecture. What we used to call a "tock."
2. New process, what we used to call a "tick."
3. Increase core count ie Coffee Lake Refresh.
4. Increase clocks ie Kaby Lake Refresh.

Now the dilemma Intel sees itself in now is that Raptor Lake is already a refresh of Alder Lake, have increased increased core count and frequency, points 3 and 4 above. New architecture and new process are also off the table so the question is how to refresh a refresh for Intel?

 

[igor_kavinski]

New architecture and new process are also off the table so the question is how to refresh a refresh for Intel?

They have lots of practice doing that from the 14nm era.

 

[DrMrLordX]

New architecture and new process are also off the table so the question is how to refresh a refresh for Intel?

Remember Comet Lake? Okay, imagine that if it had only been 8c instead of 10c. There you go.

 

[Hulk]

Remember Comet Lake? Okay, imagine that if it had only been 8c instead of 10c. There you go.

You are right in that Coffee Lake Refresh to Comet Lake was one of the weakest "new" generations from Intel and probably an apt comparison to what we can expect for the Raptor Refresh.

Comet Lake brought die thinning, thermal velocity boost, favored cores, and about 300MHz clock increase, along with 10 cores at the top of the stack.

Remove the 10c and Comet was basically Coffee Lake.

The problem still remain for Intel in that it is unlikely they will be able to add cores OR increase clocks higher than the current 6GHz.

 

[Geddagod]

Getting HT to work on the e cores, imho, is a lot more important than avx512, especially as intel plans based on rumors, to leverage altera among other acquisitionary ip into their future hardware. avx512 while legitimate and having a use has sadly become a buzzword in consumer computing and I'm exaggerating its commonality there.

HT costs a 5% die area overhead and results in a 15-30% performance benefit in common MT applications according to Intel.
However this might not apply as much to the E-cores due to the shorter pipelines and lower ability to gain extra ILP from SMT. Plus I'm assuming there's a cost overhead involved.
I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.

 

[igor_kavinski]

I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.

Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed

www.anandtech.com

Intel states that it has a Resource Director that will arbitrate cache accesses between the four cores in a cluster to ensure fairness, confirming that Intel are building these E-cores in for multi-threaded performance rather than latency sensitive scenarios where one thread might have priority.

So if they increase the thread account with SMT, each thread will have to wait longer for cache access and it will also reduce the amount of data each thread can keep in the cache before it gets evicted, necessitating an increase in cache size. So maybe that's why they had to double the E-core cluster cache size in Raptor Lake to ensure that the extra E-cores don't sit idle for too long waiting on the cache. They might be able to put in SMT in the E-core cluster but then they may need to increase the shared cache to 6 or 8MB.

The Resource Director is what's bad for E-core threads needing the full amount of the cache, like some critical game engine thread coz the RD will regularly slap it to release its clutches from the cache and let the other threads have their fair share. The E-cores are meant more for workloads where all the threads play well together.

(Feel free to poke holes in my wild theory )

 

[naukkis]

HT costs a 5% die area overhead and results in a 15-30% performance benefit in common MT applications according to Intel.
However this might not apply as much to the E-cores due to the shorter pipelines and lower ability to gain extra ILP from SMT. Plus I'm assuming there's a cost overhead involved.
I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.

HT basically cuts per core performance to half. It's pretty much opposite what they actually want for hybrid designs - so instead of adding SMT to E-core Intel should get rid of SMT from P-cores too as halving P-cores per thread performance with SMT is basically just opposite what P-cores are supposed to do - increase per thread performance. SMT makes sense for low-core count desktop/mobile solutions - but high core count cpu's should get rid of it.

 

[Saylick]

HT basically cuts per core performance to half. It's pretty much opposite what they actually want for hybrid designs - so instead of adding SMT to E-core Intel should get rid of SMT from P-cores too as halving P-cores per thread performance with SMT is basically just opposite what P-cores are supposed to do - increase per thread performance. SMT makes sense for low-core count desktop/mobile solutions - but high core count cpu's should get rid of it.

That's true only because certain structures within the core are statically partitioned into 2 halves when HT is enabled. If the partitioning of structures were done dynamically, or at least intelligently, such that the primary thread is always given enough resources, then I don't see why keeping HT couldn't still give you some benefit for super low priority background tasks that don't need even the performance or throughput of an E core.

 

[A///]

View attachment 79480

Hadn't seen that rumor but it seems to confirm that Intel is VERY predictable. They don't want to explain to investors, I guess, about why a year later they are releasing 13th gen refresh parts so they just call them 14th gen and pretend that they made a gen worth of progress.

I wasn't disagreeing with you. I took your example of 8th and 9th gen and expanded on the differences to 8 to 9 and how 13 to 13R is different. Although that's what we the general public know.

 

[A///]

HT costs a 5% die area overhead and results in a 15-30% performance benefit in common MT applications according to Intel.
However this might not apply as much to the E-cores due to the shorter pipelines and lower ability to gain extra ILP from SMT. Plus I'm assuming there's a cost overhead involved.
I don't even think HT on E-cores is a complexity problem, based on the long history of Intel using HT in their previous architectures, but rather them just not wanting to for some reason.

You've got it right there in your reply. It's a redesign and costs issue. Until Intel really needs to incorporate it they won't. If Intel could drop their power use to AMD's level then they can play the "more cores" games until AMD figures out what to do.

Trying not to raise the stupid ire of mister swagger, Intel's e cores have their usefulness and anyone who calls them fake cores is in my humble opinion a moron. No one on here has but I've seen it online. E cores have their place and usefulness. It depends on microsoft to write or improve their scheduler to accommodate the power and performance they can deliver.

intel knows avx512 takes a lot of space up and that likely less than 3% of their mainstream consumers will ever utilise it. that space is better used for more cores or accelerators that are to put it faster than avx512 with minimal thermal impact when handling data.

if amd were to ever figure out a way to stick to 16 cores, drop power and thermals while improving performance beyond a 30% leap in a magical world where jack and the beanstalk exist and unciforns poop out candy and donuts then intel would allay all resources into trying to take back the crown.

The first step in intel making ammends with itself are getting its power control under control and that's going to come into the grand mix soon within the next 2 gens.

 

[A///]

Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed

www.anandtech.com

So if they increase the thread account with SMT, each thread will have to wait longer for cache access and it will also reduce the amount of data each thread can keep in the cache before it gets evicted, necessitating an increase in cache size. So maybe that's why they had to double the E-core cluster cache size in Raptor Lake to ensure that the extra E-cores don't sit idle for too long waiting on the cache. They might be able to put in SMT in the E-core cluster but then they may need to increase the shared cache to 6 or 8MB.

The Resource Director is what's bad for E-core threads needing the full amount of the cache, like some critical game engine thread coz the RD will regularly slap it to release its clutches from the cache and let the other threads have their fair share. The E-cores are meant more for workloads where all the threads play well together.

(Feel free to poke holes in my wild theory )

Every problem is temporary. Just ask intel about their 10nm yields. Every problem has a solution. Clusters in multiples of 4 to maintain the cohesion per intel's commentary works only if you can keep power delivery and thermals in check and of course space.

There is only so much space you can use on current processor packages before you need to increase size and to increase size you run into certain issues like warp on lga1700 in some instances not all or with tr and homespoun epyc people not getting the torque right after multiple tries even though it's easier now. there is one benefit to intels upcoming approaches... they have more space than amd to play with.

although this person suspects mobo designs are going to change sometime in the next decade to accommodate larger packages and newer more slim tech. I don't foresee some of the current tech on mobos being around in 10 years in their current form but in a different form that's more respondant to real estate on the board. Or I'm a crazy old man who'll be wrong and expansion will flip to the rear of the mobo in addition to the front.

 

[DrMrLordX]

The problem still remain for Intel in that it is unlikely they will be able to add cores OR increase clocks higher than the current 6GHz.

Pretty much this. The best they can do is maybe replace some of the lower-end SKUs still using Alder Lake with a full raft of Raptor Lake products. Good for the discount buyers, maybe. And/or they can make the product stack more cost-competitive, assuming their investors will tolerate the hit to margins.

This is what happens when Intel 4/Meteor Lake is a swing and a miss on desktop.

 

[igor_kavinski]

Or I'm a crazy old man who'll be wrong and expansion will flip to the rear of the mobo in addition to the front.

Heh. Then I'm crazy too

Mini-ITX mobos already have M.2 slots on the underside of the PCB. Now they just need to redesign the ATX form factor a little bit and we can have wider cases that allow to have CPU on one side and GPU on the back side of the mobo, thus isolating their heat from each other and improving the thermals. Maybe they could call it WATX for wide ATX or Dual Sided ATX (DSATX).

 

[A///]

Heh. Then I'm crazy too

Mini-ITX mobos already have M.2 slots on the underside of the PCB. Now they just need to redesign the ATX form factor a little bit and we can have wider cases that allow to have CPU on one side and GPU on the back side of the mobo, thus isolating their heat from each other and improving the thermals. Maybe they could call it WATX for wide ATX or Dual Sided ATX (DSATX).

Go with a horizontal case then like they did up until the P4 days. I was going for more than M.2 slots. I'm not sure if putting m.2 slots on the back is wise given their ever increasing speed and thermals when hounded by read or write functions and no one wants active cooling, You soon run into problems running 2230 or 2242 even if it would save space. I've seen a few mobos where they'll have 2280sx2 in the same field and that cuts down on wastage of space. although saving space is not ideal if you need to spend excessive amounts of rd money on designing a socket that is idiot proof.

buy a good vertical case with adequate airflow in a cool room and you can get away with a high end air cooler on a hot processor such as the 13900k or the 7950x. this isn't reasonable to ask for anyone ofc.

 

[mikk]

MTL first benchmark? http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ure-lakes-rapids-thread.2509080/post-40985456

Base clock 1.2 Ghz is from an ES1 sample. InstLatX64 spotted an ES2 MTL-P 6+8 sample, the base clock is upped to 2.3 Ghz. It's still ES2 with a generic CPUID, it doesn't tell much about the shipping clock speeds. Base clock from an i7-1360P is at 2.2 Ghz right? Having 2.3 Ghz on ES2 is quite good I would say. This is nothing like Icelake-U where i7-1065G7 clocked at a measly 1.3 Ghz (base clock).

https://twitter.com/x/status/1647504366251679744

 

[Hulk]

Base clock 1.2 Ghz is from an ES1 sample. InstLatX64 spotted an ES2 MTL-P 6+8 sample, the base clock is upped to 2.3 Ghz. It's still ES2 with a generic CPUID, it doesn't tell much about the shipping clock speeds. Base clock from an i7-1360P is at 2.2 Ghz right? Having 2.3 Ghz on ES2 is quite good I would say. This is nothing like Icelake-U where i7-1065G7 clocked at a measly 1.3 Ghz (base clock).

https://twitter.com/x/status/1647504366251679744

I agree, this isn't all doom and gloom. While it would be nice if Intel could move from one process to the next and be able to bring the 1st commercial release of the new process to market at comparable speeds as the last iteration of the previous process it simply isn't possible for them. Intel does have a good track record of successfully ramping clocks if we look at 14nm and 10nm, both of which had severe teething problems but eventually reached quite high clocks and good efficiency if run in a sane portion of the v/f curve.

Intel needs a mobile release of MTL in order to work out how to ramp up clocks for desktop. It's not the end of the world for them. Raptor is quite competitive with Zen 4 from a performance and pricing point-of-view if not for efficiency. And even when it comes to efficiency, someone running day-to-day tasks like office apps and even gaming isn't going to see a meaningful difference in their electric bill if running a 13600 vs a 7700.

With that being said if you are going to compress video for hours on end or run a DC farm then yes, Zen 4 is the way to go.

Anyway since it seems as though MTL is very much like RPL this is more like a good old fashioned die shrink more than anything else. It's Broadwell mobile or Ice Lake again. Intel can use these parts for mobile while keeping the 10nm fabs going during the transition to Intel 4. It keeps production fully utilized and reduces risk. It's the safe thing big companies usually do. No big bets on Intel 4 out of the gate.

 

[mikk]

Anyway since it seems as though MTL is very much like RPL this is more like a good old fashioned die shrink more than anything else. It's Broadwell mobile or Ice Lake again. Intel can use these parts for mobile while keeping the 10nm fabs going during the transition to Intel 4. It keeps production fully utilized and reduces risk. It's the safe thing big companies usually do. No big bets on Intel 4 out of the gate.

Much higher efficiency is very much like RPL? RPL has a high idle consumption which really hurts for mobile, MTL can improve on this and also graphics performance. If MTL comes for desktop it likely comes together with ARL-S and much later than mobile.

 

[BorisTheBlade82]

Much higher efficiency is very much like RPL? RPL has a high idle consumption which really hurts for mobile, MTL can improve on this and also graphics performance. If MTL comes for desktop it likely comes together with ARL-S and much later than mobile.

Do you have any numbers like for like?
Even if, too much idle consumption is design-induced for RTL. By going from monolithic to tile-based, it can - per definitionem - only go backwards. Interesting to see, if they will improve significantly.

 

[Thunder 57]

I agree, this isn't all doom and gloom. While it would be nice if Intel could move from one process to the next and be able to bring the 1st commercial release of the new process to market at comparable speeds as the last iteration of the previous process it simply isn't possible for them. Intel does have a good track record of successfully ramping clocks if we look at 14nm and 10nm, both of which had severe teething problems but eventually reached quite high clocks and good efficiency if run in a sane portion of the v/f curve.

Intel needs a mobile release of MTL in order to work out how to ramp up clocks for desktop. It's not the end of the world for them. Raptor is quite competitive with Zen 4 from a performance and pricing point-of-view if not for efficiency. And even when it comes to efficiency, someone running day-to-day tasks like office apps and even gaming isn't going to see a meaningful difference in their electric bill if running a 13600 vs a 7700.

With that being said if you are going to compress video for hours on end or run a DC farm then yes, Zen 4 is the way to go.

Anyway since it seems as though MTL is very much like RPL this is more like a good old fashioned die shrink more than anything else. It's Broadwell mobile or Ice Lake again. Intel can use these parts for mobile while keeping the 10nm fabs going during the transition to Intel 4. It keeps production fully utilized and reduces risk. It's the safe thing big companies usually do. No big bets on Intel 4 out of the gate.

For many like me I don't think it's so much about the electric bill. I really don't care about that as it's rather small. It's about the amount ofheat that is getting dumped into the room. For some people that may be a good thing. For me, it is not.

 

[igor_kavinski]

While it would be nice if Intel could move from one process to the next and be able to bring the 1st commercial release of the new process to market at comparable speeds as the last iteration of the previous process it simply isn't possible for them.

Intel being in panic mode to compete with AMD's process advantage is making things worse for them. I think bringing a brand new architecture on a new process is extremely risky for them. They could have released ADL-N parts on Intel 4 first to get some much needed experience with the new process technology. Instead, they are going to end up with a lot of ambitious firsts with MTL. Stupid move or ballsy move, depending on the final outcome.

 

[Thunder 57]

Intel being in panic mode to compete with AMD's process advantage is making things worse for them. I think bringing a brand new architecture on a new process is extremely risky for them. They could have released ADL-N parts on Intel 4 first to get some much needed experience with the new process technology. Instead, they are going to end up with a lot of ambitious firsts with MTL. Stupid move or ballsy move, depending on the final outcome.

Hadn't thought of it that way, but it's like throwing a deep ball in a big game. If the catch is made you look like a genius, if it is dropped or picked off people are questioning if you are the right man for the job.

 

[Geddagod]

Intel being in panic mode to compete with AMD's process advantage is making things worse for them. I think bringing a brand new architecture on a new process is extremely risky for them. They could have released ADL-N parts on Intel 4 first to get some much needed experience with the new process technology. Instead, they are going to end up with a lot of ambitious firsts with MTL. Stupid move or ballsy move, depending on the final outcome.

Wasn't that just loihi 2?

 

[Hulk]

Intel being in panic mode to compete with AMD's process advantage is making things worse for them. I think bringing a brand new architecture on a new process is extremely risky for them. They could have released ADL-N parts on Intel 4 first to get some much needed experience with the new process technology. Instead, they are going to end up with a lot of ambitious firsts with MTL. Stupid move or ballsy move, depending on the final outcome.

Until we get some IPC comparisons of MTL vs RPL we don't know how "new" MTL actually is.