Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[igor_kavinski]

Wasn't that just loihi 2?

True. However, it's a tiny chip and not something that has probably shipped in volume. Maybe few thousand chips shipped to universities around the world? It's also not a general purpose CPU.

 

[jpiniero]

They could have released ADL-N parts on Intel 4 first to get some much needed experience with the new process technology. Instead, they are going to end up with a lot of ambitious firsts with MTL. Stupid move or ballsy move, depending on the final outcome.

The 2+8 tile is just 40 mm2 IIRC. And the 6+8 tile is probably roughly 60 mm2. They should be able to salvage most tiles all the way down to 1+4 even assuming yields are super crappy. They could also throw in some Raptor Lake rebrands if need be.

 

[Exist50]

They could have released ADL-N parts on Intel 4 first to get some much needed experience with the new process technology.

Supposedly they had pretty much exactly that on the roadmap at one point, but they canceled it to pull the engineers into Meteor Lake. Also around the same time as the 7nm/Intel 4 delay, which probably factored in.

Instead, they are going to end up with a lot of ambitious firsts with MTL.

I think from an Intel 4 perspective, at least, Meteor Lake makes it as low risk as possible. They have what? 4-ish major IPs on the die? And only ~1 of them is analog-y? Definitely a far narrower scope than a full shrink of ADL-N.

 

[Geddagod]

Supposedly they had pretty much exactly that on the roadmap at one point, but they canceled it to pull the engineers into Meteor Lake. Also around the same time as the 7nm/Intel 4 delay, which probably factored in.

I think from an Intel 4 perspective, at least, Meteor Lake makes it as low risk as possible. They have what? 4-ish major IPs on the die? And only ~1 of them is analog-y? Definitely a far narrower scope than a full shrink of ADL-N.

I would fully believe if people said Intel 4 is yielding terribly because Intel switched back from 4 fin to 3 fin for RWC lol , it's not completely low risk

 

[igor_kavinski]

I'm not a semicon engineer but it seems weird that a straight up optical shrink would be more risky.

 

[DrMrLordX]

Wasn't that just loihi 2?

Yeah but

True. However, it's a tiny chip and not something that has probably shipped in volume. Maybe few thousand chips shipped to universities around the world? It's also not a general purpose CPU.

Last I heard, it was to select beta testers (or similar). You are correct in asserting that it was never meant to be high-volume or commercially-available. And Loihi 2 is tiny.

 

[Exist50]

I'm not a semicon engineer but it seems weird that a straight up optical shrink would be more risky.

An "optical shrink" refers to using the same physical design/layout, and just tweaking the optics used to shrink it. When shrinking a full node, however, that doesn't work (or at least not these days); you need to redesign your transistor layout to adjust to the new node's characteristics.

It's a decent amount of work even for digital circuits, but for analog ones, where you're very dependent on process characteristics, it sets you back much further. For the same reason, those circuits are the most susceptible to problems from an unstable node.

Seems to me that Intel went to great lengths to move (almost) all of the analog IPs off of Intel 4 to reduce their process risk as much as possible, but I can't help but wonder if they introduced too much design risk in doing so.

 

[Doug S]

An "optical shrink" refers to using the same physical design/layout, and just tweaking the optics used to shrink it. When shrinking a full node, however, that doesn't work (or at least not these days); you need to redesign your transistor layout to adjust to the new node's characteristics.

It's a decent amount of work even for digital circuits, but for analog ones, where you're very dependent on process characteristics, it sets you back much further. For the same reason, those circuits are the most susceptible to problems from an unstable node.

Seems to me that Intel went to great lengths to move (almost) all of the analog IPs off of Intel 4 to reduce their process risk as much as possible, but I can't help but wonder if they introduced too much design risk in doing so.

Yep my understanding is that a process has to be specifically designed to be design rule compatible with a previous process for optical shrinks to be possible. i.e. stuff like TSMC N6 and N4, which TSMC took care to insure could take existing N7+ (AFAIK you can't do an optical shrink of N7 -> N6 only N7+ -> N6) and N5 designs and get slightly better power, area, etc.

These are very small shrinks, it was like 6% for N5 -> N4 for example, but that's a 6% cut in your per chip cost (or better as N4 was expected to yield slightly better than N5) so customers are happy to take it since it is "free" in terms of no need for redesign or spending millions on new mask sets.

 

[H433x0n]

So why would ARL-S be on TSMC N3 if Meteor Lake has a base clock similar to Tiger Lake?

Couldn’t they do ARL-S on Intel 3 if Meteor Lake is able to hit similar clocks to Tiger Lake?

 

[Hulk]

I did a little research on those $150 million dollar EUV's. Insane technology. It could be argued they are a larger achievement than landing a man on the moon.

It's no wonder creating these parts is so tricky.

 

[BorisTheBlade82]

I did a little research on those $150 million dollar EUV's. Insane technology. It could be argued they are a larger achievement than landing a man on the moon.

It's no wonder creating these parts is so tricky.

Exactly. And it is a shame, that 99% of world's population still thinks, that rocket science would be a big thing.

 

[Thunder 57]

I did a little research on those $150 million dollar EUV's. Insane technology. It could be argued they are a larger achievement than landing a man on the moon.

It's no wonder creating these parts is so tricky.

I want to disagree since I am a space nerd, but it's pretty hard to. I've generally considered the design and manufature of CPU's the most challenging thing humans have ever done.

 

[Hulk]

I want to disagree since I am a space nerd, but it's pretty hard to. I've generally considered the design and manufature of CPU's the most challenging thing humans have ever done.

I'm a space nerd to. Besides belonging to the Princeton Astronomical Society I also built a model of New Horizons with my daughter when she was in 1st grade!
That's why I wrote arguably. The moon landing was just as insane as these EUV's. That either can be done is just ridiculous.

 

[Doug S]

I did a little research on those $150 million dollar EUV's. Insane technology. It could be argued they are a larger achievement than landing a man on the moon.

It's no wonder creating these parts is so tricky.

That's what people saying "oh China will just steal the blueprints for EUV machines and have their own in a couple years" don't realize. It isn't enough to have the blueprints, ASML has hundreds of subcontractors making parts that they had to invent manufacturing techniques for. And many of those subcontractors have their own subcontractors. China could have the exact blueprints and a working EUV machine to examine and probably couldn't replicate the technology before the end of the decade. They may be more likely to find a different path to making leading edge chips than they are to copy existing EUV technology.

Not sure how much of their research involves trying to copy EUV than trying to make other technologies workable for mass production like e-beam.

 

[Geddagod]

So why would ARL-S be on TSMC N3 if Meteor Lake has a base clock similar to Tiger Lake?

Couldn’t they do ARL-S on Intel 3 if Meteor Lake is able to hit similar clocks to Tiger Lake?

Some people think LNC was also being designed for Intel 3 at some point as well, but ARL moved on to 20A since the node schedule allowed it. And I wouldn't be surprised if TSMC 3nm was always a target for ARL since Intel's CEO already bought a bunch of 3nm capacity and they would have to have used it at some point. Even back in 2020 Intel was stating they would need to outsource for their products, so I don't think switching over to TSMC 3nm was a reactionary step but always part of the plan since near inception for ARL's design. Using it in earlier products, such as MTL, doesn't make much sense since 3nm would not have been ready for it. Using it after ARL doesn't make sense either since Intel would have moved on to Intel 18A at the least, at which point they should be ahead of TSMC 3nm.
Honestly using TSMC 3nm instead of Intel 20A to me doesn't make much sense to me either, unless A) they needed ARL out earlier so they went for TSMC 3nm (at which point why not Intel 3?), B) They wanted to use HD libs (but why on desktop and not mobile?) C) They think 20A is going to clock too low at the top of the v/f curve (most likely one IMO) D) costs (is Intel 3/Intel 20A really that expensive that outsourcing to a external node is cheaper?)

 

[BorisTheBlade82]

That's what people saying "oh China will just steal the blueprints for EUV machines and have their own in a couple years" don't realize. It isn't enough to have the blueprints, ASML has hundreds of subcontractors making parts that they had to invent manufacturing techniques for. And many of those subcontractors have their own subcontractors. China could have the exact blueprints and a working EUV machine to examine and probably couldn't replicate the technology before the end of the decade. They may be more likely to find a different path to making leading edge chips than they are to copy existing EUV technology.

Not sure how much of their research involves trying to copy EUV than trying to make other technologies workable for mass production like e-beam.

Couldn't agree more.
IIRC it was stated somewhere, that China would need until around 2035 in order to just get a comparable process up and running on their own as what TSMC has at hand today - 5nm.

 

[Exist50]

Couldn't agree more.
IIRC it was stated somewhere, that China would need until around 2035 in order to just get a comparable process up and running on their own as what TSMC has at hand today - 5nm.

We should probably move this discussion to another thread, but ASML's CEO was quoted a couple years back as saying that, if forced, it would take China ~15 years to replace them for good. If that timeline were to hold, they'd be well past 5nm by 2035.

 

[Exist50]

Some people think LNC was also being designed for Intel 3 at some point as well, but ARL moved on to 20A since the node schedule allowed it. And I wouldn't be surprised if TSMC 3nm was always a target for ARL since Intel's CEO already bought a bunch of 3nm capacity and they would have to have used it at some point. Even back in 2020 Intel was stating they would need to outsource for their products, so I don't think switching over to TSMC 3nm was a reactionary step but always part of the plan since near inception for ARL's design. Using it in earlier products, such as MTL, doesn't make much sense since 3nm would not have been ready for it. Using it after ARL doesn't make sense either since Intel would have moved on to Intel 18A at the least, at which point they should be ahead of TSMC 3nm.
Honestly using TSMC 3nm instead of Intel 20A to me doesn't make much sense to me either, unless A) they needed ARL out earlier so they went for TSMC 3nm (at which point why not Intel 3?), B) They wanted to use HD libs (but why on desktop and not mobile?) C) They think 20A is going to clock too low at the top of the v/f curve (most likely one IMO) D) costs (is Intel 3/Intel 20A really that expensive that outsourcing to a external node is cheaper?)

With Lunar Lake looking pseudo-monolithic, even without any N3 commitments, it would be difficult for them to switch. Just moving ARL to Intel 3 and leaving LNL on N3 would mean producing Lion Cove on three entirely different nodes all around the same time period. For a team that historically has only done one node, that would be a tall ask.

And besides, N3 is just the straight up better node. Realistically, Intel 3 is going to be more of an N4 competitor.

 

[H433x0n]

Honestly using TSMC 3nm instead of Intel 20A to me doesn't make much sense to me either, unless A) they needed ARL out earlier so they went for TSMC 3nm (at which point why not Intel 3?), B) They wanted to use HD libs (but why on desktop and not mobile?) C) They think 20A is going to clock too low at the top of the v/f curve (most likely one IMO) D) costs (is Intel 3/Intel 20A really that expensive that outsourcing to a external node is cheaper?)

Well, I'm not sure if N3X will be out in time for ARL-S. Unless they plan on using N3E for ARL-S. Even assuming N3X is ready for a ARL-S release that meets the deadline of 1H 2024, it's going to be extremely expensive. TSMC"s wafer costs are already obscenely expensive for N5, I don't see how N3 is an attractive proposition. I just don't get the logic of it unless their internal fabs were unable to satisfy their stated deadlines and based on current data (leaks & ES2 silicon) MTL-S seems to be meeting the frequency targets.

And besides, N3 is just the straight up better node. Realistically, Intel 3 is going to be more of an N4 competitor.

Do you have any data on this? The data on the Intel 3 node is really sparse. Based on the data I can find for the Intel 4 process, it seems like Intel 3 would be an improvement over N3 in logic but behind in memory density (assuming Intel 3 is at least ~10% better than Intel 4).

 

[Geddagod]

With Lunar Lake looking pseudo-monolithic, even without any N3 commitments, it would be difficult for them to switch. Just moving ARL to Intel 3 and leaving LNL on N3 would mean producing Lion Cove on three entirely different nodes all around the same time period. For a team that historically has only done one node, that would be a tall ask.

And besides, N3 is just the straight up better node. Realistically, Intel 3 is going to be more of an N4 competitor.

Past SNC I'm assuming, Intel started developing their architectures way more node agnostically. Gracemont, for example, looks to have been planned to use Intel 4

and then ported to Intel 7, very early on in design. It also makes sense with their design strat, being Palm Cove on new Intel 10nm, SNC being the new architecture on Intel 10nm+, Willow Cove being SNC on Intel 7nm, then GLC being the new architecture on Intel 7nm along with Gracemont. It also explains why Intel cores have just been huge recently relative to perf as well.

But beyond that, I don't think LNC on Intel 3 really would have gone anywhere, other than being a backup plan, early into the design schedule. Sort of like RKL was planned up to be in 2019, which according to Cheese had mobile skus planned too in the 'in the worst case scenario push red button' of 10nm never being fixed. Which is why when Pat mentioned GNR using a new core from RWC, I was a bit surprised. It doesn't necessarily mean LNC in GNR, could be RWC+, but who knows. These decisions for LNC would have started in around 2021 or even earlier, which coincidentally would have been around the time Intel announced that their 7nm would be delayed even further. It makes sense Intel would want to mitigate as much risk as possible.
TSMC 3nm would always have been in the plans though, and the only point of contention would have been using Intel 3 or Intel 20A, and I think them using Intel 20A was the original plan anyway since that would put them back on track to their 'tick tock' strategy following Palm Cove. It would have been hard, yes, but it's not like Intel hadn't had plenty of time due to all their node delays and refreshes. And it's not like we have seen speedy backports done in the past (RKL) or scrapped architectures (Ocean Lake).

This is of course all just theory crafting, but I think it's all possible within the Intel timeline, if not what actually happened.

 

[Exist50]

Past SNC I'm assuming, Intel started developing their architectures way more node agnostically. Gracemont, for example, looks to have been planned to use Intel 4

Not quite. Atom has been node agnostic since at least Goldmont. Big core is only node agnostic starting from Lion Cove. That image shown there also predates Crestmont's existence on the roadmap.

But beyond that, I don't think LNC on Intel 3 really would have gone anywhere, other than being a backup plan, early into the design schedule.

Well if we do assume that they intended for GNR to use Lion Cove on Intel 3, then that would make it far more important. But if/when they settled on RWC, that would have significantly diminished the necessity of porting Lion Cove to another node, with ripple effects to client. Though maybe that freed them up enough to bring it to 20A.

TSMC 3nm would always have been in the plans though, and the only point of contention would have been using Intel 3 or Intel 20A, and I think them using Intel 20A was the original plan anyway since that would put them back on track to their 'tick tock' strategy following Palm Cove.

Arrow Lake was originally targeted in the 2023-ish timeframe, but it's also been pushed back, seemingly enough for them to intercept 20A at the tail end. Though I'd guess a MTL derivative using 20A was always the plan in some form or another. Too convenient an opportunity to pass up.

 

[Geddagod]

Not quite. Atom has been node agnostic since at least Goldmont. Big core is only node agnostic starting from Lion Cove. That image shown there also predates Crestmont's existence on the roadmap.

Well if we do assume that they intended for GNR to use Lion Cove on Intel 3, then that would make it far more important. But if/when they settled on RWC, that would have significantly diminished the necessity of porting Lion Cove to another node, with ripple effects to client. Though maybe that freed them up enough to bring it to 20A.

Arrow Lake was originally targeted in the 2023-ish timeframe, but it's also been pushed back, seemingly enough for them to intercept 20A at the tail end. Though I'd guess a MTL derivative using 20A was always the plan in some form or another. Too convenient an opportunity to pass up.

I genuinely think GLC was not meant to be on a 7nm node. It's way too chonky imo.
GLC, for a 2021 release, the core itself would have started to have been drawn up in 2017-2018ish, with the CPU development itself being started late/mid 2018.
During 2018, I think Intel were still expecting they could iron out their node issues and were still expecting this schedule:
Palm Cove – Intel 10nm 2018
Sunny Cove – Intel 10nm+ 2019
Willow Cove – Intel 10nm++ 2020
Golden Cove – Intel 7nm (desirable) or Intel 10nm+++ (backport) 2021
This is supported by this graph given in 2018 architecture day

and matching up the years to the foundry roadmap given in 2019

Adding some annotations

I think Intel had Golden Cove in mind for the "backport opportunity" and took it in Alder Lake when they realized that Intel 7nm EUV was not going to pan out in 2021 at all.
The timing of when they decided to port Golden Cove to 10nm+++ rather than 7nm was prob early/mid 2018, and by 2019 they probably were still hoping that redwood cove would be able to come out in late 2022 so they could show how GLC was the backport to Intel 10nm+++, hence the backport opportunity, while RWC would be on the actual 7nm node with a tick architecture.
And prob why it didn't end up with RKL levels of bad performance might be because GLC could have been designed in mind with the possibility it may have to be ported, or because the Israel team essentially did all of GLC, while for the SNC backport, the Indian team which would have been newer, handled it.
Also could help explain how RPL was able to get such a sizable clock improvement over ADL, without the node being changed nearly as much. Way better DTCO considering GLC might not have been fully baked.

 

[Geddagod]

But for ARL, what could have potentially happened:

LNC started development late 2019 for Intel 7nm and TSMC 3nm. This should be ready ~ late 2020, early 2021.
Hence we see the mid-late 2023 ARL-P leaks on TSMC 3nm.
Intel realigns roadmaps and foundries internally around late 2020/ early 2021. Announced to the public in mid 2021.
LNC gets 'redefined', starts development of 20A for a 2024 launch around early 2021. TSMC delays also ensured that their original 2023 launch date is unrealistic.
The core is ready by early 2022. This follows Xeno's leak of LNC being design frozen early 2022 (maybe for the 20A variant?)
ARL with LNC on 20A comes late, late 2024 or 2025, with the TSMC 3nm variants coming out around half a year to a year earlier.

This could explain how GNR is able to change core design to LNC so relatively quickly after only ~1 year delay from original release date. LNC's Intel 7nm development could already have had a lot of work done.

However two counter points to this could be:
1) LNC was always planned on Intel 20A, since Intel also thought Intel 20A would be ready by 2023 all the way back in 2019
2) LNC wasn't planned for any internal Intel nodes until early 2021, and was only planned for TSMC since late 2019.

Something to note about GNR though is that half way through 2021 Intel were still claiming GNR would be on Intel 4. Assuming that Intel switched tack to Intel 3 as soon as possible 2H 2021, they would need the development of the CPU to start essentially as soon as they switched, with little to no time to develop a core design.
However if Intel were designing LNC for Intel 7nm/Intel 3 from the start, they already would have LNC ready for the server team...

Schedule would be a tight fit but I think it's possible. Only problem is believing Intel would have so many separate design teams working all at the same time.
Very excited to see if we get any more info in a week during Intel's q1 earnings call

 

[A///]

cliff notes version gedda...

 

[Exist50]

I think Intel had Golden Cove in mind for the "backport opportunity" and took it in Alder Lake when they realized that Intel 7nm EUV was not going to pan out in 2021 at all.

As far as I'm aware, Golden Cove was always intended to be on 10nm, with the first 7nm product intended to be an aforementioned Atom-based pipecleaner going into production at the way end of the 2021. And if you look at the delta for Golden Cove vs Sunny Cove, GLC isn't really bad. It's big, sure, but the gen/gen change isn't anything particularly crazy. The problem is that SNC baseline is terrible.

And prob why it didn't end up with RKL levels of bad performance might be because GLC could have been designed in mind with the possibility it may have to be ported, or because the Israel team essentially did all of GLC, while for the SNC backport, the Indian team which would have been newer, handled it.

I think RKL's failure gets attributed to the wrong things. Far as I can see, the backport of Sunny Cove itself was perfectly fine. The problems were twofold.

1) They also backported the ICL uncore, which gave us the memory latency issues that hurt gaming so much. Probably also a contributing factor to the 8c limit.

2) Sunny Cove itself was a disaster. If you look at how much extra area and power it burns for the IPC it delivered, Sunny Cove was an absolutely terrible architecture, and made worse by how long it took to deliver. 10nm absorbed much of the blame for Ice Lake, and both process improvements and some tuning of the core salvaged it for Tiger Lake, but Rocket Lake laid bare its flaws.