Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Exist50]

Good spot.
It is quite surprising, that these schematics seem to represent a real product. Is this just laziness in Intel's patent department? Usually everyone plays the Hide & Seek game.

Yeah, it's pretty funny that they've just had that sitting in the open for who knows how long now. Presumably patent applications go through legal, but not marketing. Someone found a loophole, lol.

But ultimately, don't think it really matters. Intel's done a pretty poor job of keeping Meteor Lake secret. Too many MTL refugees floating around to keep things quiet, imo.

 

[Exist50]

Yep, exactly. This has been rumoured for a long time already. Up until now it wasn't that clear what kind of core this would be and how many of them. 2 Atom cores do sound like a good idea for heavy idle (AV, Cloud Sync, Background updates etc.)

I mentioned what I thought to be the config a while ago, but it's good to get real confirmation. http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...-rapids-thread.2509080/page-619#post-40743174

I think on paper, the idea is good. Will have to see how it works out in practice. They've added yet another layer of scheduling complexity, but hopefully they've had enough time to sort out the implications there with Microsoft.

 

[Geddagod]

Wait wait wait. So we are going to be seeing crestmont on Intel 4 AND TSMC 5nm? This is going to be fun
Only problem is idk if Intel is going to provide a die shot of the SOC tile, they are pretty good at providing die shots when asked though...
Also I really hope the crestmont on the soc tile will be the same as the one on the CPU tile design wise. Idk if Intel would want to put in the extra resources into changing core design for the SOC tile.

 

[mikk]

Around a year

We cannot rule out a launch in Q2 2024 right? Of course if they have to wait for ARL-S they might have to delay it.

 

[Henry swagger]

Wait wait wait. So we are going to be seeing crestmont on Intel 4 AND TSMC 5nm? This is going to be fun
Only problem is idk if Intel is going to provide a die shot of the SOC tile, they are pretty good at providing die shots when asked though...
Also I really hope the crestmont on the soc tile will be the same as the one on the CPU tile design wise. Idk if Intel would want to put in the extra resources into changing core design for the SOC tile.

This the first intel cpu ip on a tsmc node ?

 

[A///]

Early Platform Hardening Technology For Slimmer And Faster Boot Patent Application

U.S. Patent Application 20210081538 for Early Platform Hardening Technology For Slimmer And Faster Boot

uspto.report

Money quote:
"Next generation client SoC architectures may introduce large on-package caches, which will allow novel usages. Access time for the L4 (e.g., "Adamantine" or "ADM") cache may be much less than the DRAM access time"

that makes more sense than adamantium which is a term used in marvel comics and film. large difference between it and the correct term adamantine. i look forward to the performance if it comes to client systems.

 

[A///]

Too many MTL refugees floating around to keep things quiet, imo.

??????????????????

 

[Henry swagger]

Intel Reportedly Begins Emerald Rapids & Meteor Lake-S Desktop CPU Sampling, 5th Gen Xeon Pictured

Intel has reportedly started sampling its 5th Gen Emerald Rapids and Meteor Lake-S Desktop CPUs as revealed in a recent document.

wccftech.com

Meteor lake is coming on desktop 😏

 

[AMDK11]

Maybe Meteorlake-S will actually be such a big positive surprise that Intel is so careful about the details. At worst, it will be bad or so-so.

RaptorLake refreshed may be a nod to LGA1700 as Meteorlake-S will be on LGA1851.

 

[BorisTheBlade82]

They've added yet another layer of scheduling complexity, but hopefully they've had enough time to sort out the implications there with Microsoft.

Yep, my line of thinking as well.
They will need a pretty big treshold in order to not switch over to the compute tile too soon and much. But also not too high in order to stay snappy.

 

[Exist50]

that makes more sense than adamantium which is a term used in marvel comics and film. large difference between it and the correct term adamantine.

They're the same root. I've heard both used.

??????????????????

Intel's lost many employees since Meteor Lake started. They're everywhere now, and some are willing to talk about little details with their new coworkers.

 

[Exist50]

Wait wait wait. So we are going to be seeing crestmont on Intel 4 AND TSMC 5nm? This is going to be fun

Intel 4 vs TSMC N6, and as I mentioned in that old post, there are other considerations that will invalidate a true 1:1 comparison. Doubt that will stop anyone, however.

 

[nicalandia]

Intel Reportedly Begins Emerald Rapids & Meteor Lake-S Desktop CPU Sampling, 5th Gen Xeon Pictured

Intel has reportedly started sampling its 5th Gen Emerald Rapids and Meteor Lake-S Desktop CPUs as revealed in a recent document.

wccftech.com

Meteor lake is coming on desktop 😏

As a Rebranded Raptor Cove core SKUs...

 

[Exist50]

As a Rebranded Raptor Cove core SKUs...

No, as actual Meteor Lake.

 

[AMDK11]

Is it a combination of RaptorCove + Crestmont cores?

 

[nicalandia]

Is it a combination of RaptorCove + Crestmont cores?

No, just your average Raptor Cove/RaptorMont Combination, just rebranded like 90% of Raptor Lake SKUs that while coded as Raptor Lake were fitted with Golden Cove cores

 

[AMDK11]

I doubt Raptor Lake was renamed Meteor Lake. RaptorLake, although using x86 GoldenCove, is mainly a L2 change from 1.25MB in GoldenCove to 2MB in RaptorCove.

What would Meteorlake be if it actually uses RaptorLake?

 

[nicalandia]

I doubt Raptor Lake was renamed Meteor Lake. RaptorLake, although using x86 GoldenCove, is mainly a L2 change from 1.25MB in GoldenCove to 2MB in RaptorCove.

What would Meteorlake be if it actually uses RaptorLake?

Not just the L2 on the P cores, but the e cores are also OG Gracemont with only 2 MiB shared L2$.

The rebranded SKU will have 2 MiB L2$ on P cores and 4 MiB of shared L2$ per Cluster.

 

[AMDK11]

Yes. I didn't write that Gracemont in Raptorlake got 4MB L2 on a 4 core cluster with 2MB in AlderLake.

Still, I doubt Meteorlake-S is a renamed RaptorLake.

Anyway, you'll find out in a while that the Meteorlake-S sample is RedwoodCove+Crestmont

Edit:
RedwoodCove is not the same as Golden/RaptorCove though I don't know to what extent it has been redesigned.

 

[Exist50]

Not just the L2 on the P cores, but the e cores are also OG Gracemont with only 2 MiB shared L2$.

The rebranded SKU will have 2 MiB L2$ on P cores and 4 MiB of shared L2$ per Cluster.

nicalandia, not a single source has claimed that Raptor Lake will be rebranded as desktop Meteor Lake.

 

[nicalandia]

nicalandia, not a single source has claimed that Raptor Lake will be rebranded as desktop Meteor Lake.

Its pretty much a given that MTL-S is 14th gen are going to be Raptor Lake Refresh and only the Mobile MTL will be based on Lion Cove cores

 

[ondma]

Intel Reportedly Begins Emerald Rapids & Meteor Lake-S Desktop CPU Sampling, 5th Gen Xeon Pictured

Intel has reportedly started sampling its 5th Gen Emerald Rapids and Meteor Lake-S Desktop CPUs as revealed in a recent document.

wccftech.com

Meteor lake is coming on desktop 😏

Well, that is WCCF Tech though. Take it with some skepticism. Will be interesting to see how RL Refresh, ML and AL shake out on desktop, if they all are produced.

 

[AMDK11]

Its pretty much a given that MTL-S is 14th gen are going to be Raptor Lake Refresh and only the Mobile MTL will be based on Lion Cove cores

There are no LionCove cores in Meteorlake! Meteorlake are x86 RedwoodCove cores.

LionCove is supposed to be in ArrowLake!

If I don't know something, enlighten me.

 

[Exist50]

Its pretty much a given that MTL-S is 14th gen are going to be Raptor Lake Refresh and only the Mobile MTL will be based on Lion Cove cores

No, the claim is that 14th gen desktop will be Raptor Lake refresh, but that MTL-S will also exist, and arrive alongside Arrow Lake, likely on the low end.

 

[nicalandia]

No, the claim is that 14th gen desktop will be Raptor Lake refresh, but that MTL-S will also exist, and arrive alongside Arrow Lake, likely on the low end.

I was out of that loop...