Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[msj10]

They don't always announce the tape in/tapeout of future CPUs though, they did on Icelake and Meteor Lake. I'm not aware of other announcements in the past.

they did it for Lunar Lake too

 

[uzzi38]

Arrow Lake-S 平台回歸到 Intel 在 2024 桌上型電腦處理器產品規劃中 - BenchLife.info

Arrow Lake-S 的消息又跳出來了，而 Meteor Lake-S 現在可能消失。 Inte […]

benchlife.info

It's a little off I think. ARL-S on 20A during H1 2024 is not realistic. Maybe they are just assuming it's 20A because roadmaps usually don't say what node it uses. Or they are mixing it up with MTL-S. 6+16 cancelled, means 6+8 could still come.

They misunderstood the roadmap, but based off of the other things they said I do genuinely think they have access to a roadmap.

 

[mikk]

they did it for Lunar Lake too

Arrow and Lunar share the same Mont and Cove cores.

 

[igor_kavinski]

Quoting from here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/zen4-3d-review-thread.2610878/post-40972537

What are these people going to say in a few generations when Intel goes full chiplet and relies on their interconnect designs to make it work.

Is there any evidence that they have an interconnect design that could match or even surpass what AMD has in Zen 4?

AMD had the advantage of having Bulldozer as such a bad design for its time that it was easier for them to adopt the chiplet strategy and start afresh. Intel is in the unenviable position of trying to outdo their pretty good Raptor Lake IPC with their first ever mainstream chiplet based design.

It's a monumental task for them to ensure that they manage better IPC while also offsetting the memory latency regression. RPL-R is just proof that they were wildly overconfident in their ability to overcome the challenges associated with moving to chiplet based architecture. Question is, is the time they will buy in the process going to be enough for them to meet, let alone beat, consumer as well as investor expectations?

I wish their internal Plan B document would get leaked, giving us some visibility into the possibility of a 2nd refresh of Raptor Lake (bigger package on a new socket, more cores, more cache, stock TDP 350W!) to buy time while they iron out the chiplet related performance issues.

 

[A///]

Is there any evidence that they have an interconnect design that could match or even surpass what AMD has in Zen 4?

Only if someone has the gritty details about what they've deployed in their multi chip glued xeons. other than that nothing but what was brought up in their intel day a year or two ago. zen 4 won't be the competitor to intel's chiplets then. We're still a good 2-4 years away regardless of what intel says. AMD could be on zen 6 or 6x3d by then.

 

[igor_kavinski]

We're still a good 2-4 years away regardless of what intel says. AMD could be on zen 6 or 6x3d by then.

I find your lack of faith disturbing

 

[A///]

I find your lack of faith disturbing

Last week I was on AMD payroll, this week harry may think I'm on intel's payroll. Gotta keep it fresh.

 

[Geddagod]

Quoting from here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/zen4-3d-review-thread.2610878/post-40972537


Is there any evidence that they have an interconnect design that could match or even surpass what AMD has in Zen 4?

AMD had the advantage of having Bulldozer as such a bad design for its time that it was easier for them to adopt the chiplet strategy and start afresh. Intel is in the unenviable position of trying to outdo their pretty good Raptor Lake IPC with their first ever mainstream chiplet based design.

It's a monumental task for them to ensure that they manage better IPC while also offsetting the memory latency regression. RPL-R is just proof that they were wildly overconfident in their ability to overcome the challenges associated with moving to chiplet based architecture. Question is, is the time they will buy in the process going to be enough for them to meet, let alone beat, consumer as well as investor expectations?

I wish their internal Plan B document would get leaked, giving us some visibility into the possibility of a 2nd refresh of Raptor Lake (bigger package on a new socket, more cores, more cache, stock TDP 350W!) to buy time while they iron out the chiplet related performance issues.

I fully expect Intel to not do anything different with their interconnect for if they ever end up going MCM for consumer, as in just mesh across tiles.
Intel's CPU architectures are quite literarily built for this- and the rumors point to them continuing this- massive ROBs and slower, but very big private and mid level caches compensating for higher latency L3.
Maybe the surprise would be Intel doing dual ringbus like they did way back when in server, but other than that ¯\_(ツ)_/¯

 

[deasd]

SquashBonic hint Meteor Lake might have nearly 0 ST perf changes at worst.

https://twitter.com/x/status/1638602996572647424

 

[IntelUser2000]

SquashBonic hint Meteor Lake might have nearly 0 ST perf changes at worst.

https://twitter.com/x/status/1638602996572647424

This is why Arrowlake is replacing Meteorlake at the high end. Even with 8+16 config(which isn't) essentially releasing Raptorlake again but with less power is going to do bad on desktop.

"Nearly 0 changes" sounds like the gain akin to Raptorlake. 1-3%.

@Hulk So regarding the timeline of Intel 4, SquashBonic says "this year in meme volumes" for Meteorlake. Likely that's mobile and desktop is firmly next year.

 

[igor_kavinski]

From what I can tell, MTL's saving grace might be close to RDNA3 iGPU performance (I'll assume 70% as close) and it's neural accelerator that might be fully compatible with the rumored AI features of Windows 12. Power consumption? Let's hope it's no worse than 12th gen mobile.

 

[uzzi38]

SquashBonic hint Meteor Lake might have nearly 0 ST perf changes at worst.

https://twitter.com/x/status/1638602996572647424

@BionicSquash certified "look ma get the camera" moment

 

[Geddagod]

Ye I don't think BionicSquash is a leaker though

 

[BionicSquash]

@BionicSquash certified "look ma get the camera" moment

Oh hi Uzzi

 

[BionicSquash]

Intel is still projecting Single digit improvement over RPL-P and RPL-H in benchmarks, that "Zero percent ST improvement" part is for worst case scenario where Intel might miss their targets.

SquashBonic hint Meteor Lake might have nearly 0 ST perf changes at worst.

https://twitter.com/x/status/1638602996572647424

 

[jpiniero]

Intel is still projecting Single digit improvement over RPL-P and RPL-H in benchmarks, that "Zero percent ST improvement" part is for worst case scenario where Intel might miss their targets.

By targets you probably mean clock speed. Does seem like they'd be able to get away with mixing in Raptor rebrands if it comes to that.

 

[BionicSquash]

By targets you probably mean clock speed. Does seem like they'd be able to get away with mixing in Raptor rebrands if it comes to that.

By targets, I meant Pre-si estimates over RPL-H that Intel published in internal docs for several benchmarks. You might not always Match Pre-si numbers with actual sample which is why I included the worst case scenario.

 

[inf64]

By targets, I meant Pre-si estimates over RPL-H that Intel published in internal docs for several benchmarks. You might not always Match Pre-si numbers with actual sample which is why I included the worst case scenario.

Do you know if MLID's IPC claims for Meteor Lake are true? He claimed 10-15% IPC improvement, which seems kind of high for a Golden Cove derivative.

 

[A///]

why does anyone care what that lead paint eating moron says?

 

[jpiniero]

By targets, I meant Pre-si estimates over RPL-H that Intel published in internal docs for several benchmarks. You might not always Match Pre-si numbers with actual sample which is why I included the worst case scenario.

They probally have a pretty good idea of what the IPC gains would be, right? It's mainly the clock speed that surely they have some doubts about.

 

[A///]

They probally have a pretty good idea of what the IPC gains would be, right? It's mainly the clock speed that surely they have some doubts about.

Targeting an IPC takes considerable work. Something we've seen AMD do over several generations. Today's tech allows both Intel and AMD to properly test a theory before comitting where such ability was limited a decade more ago and even further going back 20 years. Clock regression is always a serious issue but it can be tamed and often avoided.

For Intel what stands apart from them and AMD right now is their power use, anywhere from 40-110 watts more depending on the task. It'll be interesting if Intel can make some approach to this issue with the rpl refresh and later on with their outlook and new power delivery methods. That's a big if.


There's a lot riding on Gunslinger's neck over at Intel, but even so I'm interested in zen 5 next year. I've seen so much anticipation about and smoke blown up our cornholes that it's going to define the next gen of processor performance and Zen 4 was but a tiny stepping stone.

 

[Henry swagger]

Intel is still projecting Single digit improvement over RPL-P and RPL-H in benchmarks, that "Zero percent ST improvement" part is for worst case scenario where Intel might miss their targets.

So you are guessing.. what credibility do you have ?

 

[BionicSquash]

So you are guessing.. what credibility do you have ?

Zero ST improvement part is partly a guess yes based on the probability that Intel might miss their targets, but the single digit ST improvement part is not a guess, it is what Intel has been reporting with Pre-si estimates. for credibility, believing me or not is your choice

 

[Markfw]

So you are guessing.. what credibility do you have ?

And what credibility do YOU have ?

 

[mderbarimdiger]

Remind me please, what are the claims HE made?