Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[igor_kavinski]

I like DOS too. But sadly, it can be run only on VMs in UEFI systems these days.

What do you do there? Play LSL6?

 

[H433x0n]

I thought when you consider the time spent only on the SoC in many use cases the sub 30W usage was closer. But I will defer to your knowledge.

Intel "almost" caught up but are still behind in the sub 30W range.

eh, if this power curve is legit then they're pretty much caught up. It's ahead by more at 45W than it is behind at 25W. If you were to take the integral of both power curves, the MTL curve would have a higher value.

 

[Geddagod]

If possible, can you kindly elaborate on why there's so much of a difference for the same cpu?

Just diff PL2 vs PL1

Thank you so much for posting that. Very interesting.

View attachment 90493

I know there are many factors to choosing a laptop but for performance reasons, I would find it difficult not to be swayed towards AMD by that comparison. And remember, AMD has working AVX-512.

Does it at less power too, more impressively. But I would wait a couple days for more reviews, looks like Ultra is a mess for a bit. That, and I want to see the Ultra 9 or Ultra 7 165H vs the top binned AMD U part.

 

[igor_kavinski]

Does it at less power too, more impressively.

Wow. Thanks for pointing that out. Damn impressive!

 

[SiliconFly]

What do you do there? Play LSL6?

If you don't play LSL3, you're missing out passionate patti!

 

[SiliconFly]

Delete

 

[AMDK11]

No it's not, ARL compute tile taped out some time ago.

LionCove is not a secret? Have I missed something? Any data on the x86 architecture? Are there photos of the x86 core structure comparable in quality to the first photos of GoldenCove and RedwoodCove? So far, I haven't heard anything reliable about LionCove except an allegedly simulated test that says absolutely nothing about IPC, leaks and blurry photos of ArrowLake boards. The only thing that came out from what I remember are rumors that LionCove has an 8-way x86 decoder and ROB 700+. But is this real data? Nothing else is known, so in my opinion, considering a lot conflicting rumors, LionCove is one hell of an unknown when it comes to microarchitecture.

Is LionCove a redesign and expansion in the style of Skylake to SunnyCove and SunnyCove to GoldenCove? Or is it a completely different approach? If LionCove has a pipeline with fewer stages and much lower clock speeds, it will also be a different approach than SunnyCove and GoldenCove. LionCove has SMT, SMT4 or no SMT at all? Does anyone know a 99% sure answer?

 

[SiliconFly]

LionCove is not a secret? Have I missed something? Any data on the x86 architecture? Are there photos of the x86 core structure comparable in quality to the first photos of GoldenCove and RedwoodCove? So far, I haven't heard anything reliable about LionCove except an allegedly simulated test that says absolutely nothing about IPC, leaks and blurry photos of ArrowLake boards. The only thing that came out from what I remember are rumors that LionCove has an 8-way x86 decoder and ROB 700+. But is this real data? Nothing else is known, so in my opinion, considering a lot conflicting rumors, LionCove is one hell of an unknown when it comes to microarchitecture.

Is LionCove a redesign and expansion in the style of Skylake to SunnyCove and GoldenCove? Or is it a completely different approach? If LionCove has a pipeline with fewer stages and much lower clock speeds, it will also be a different approach than SunnyCove and GoldenCove. LionCove has SMT, SMT4 or no SMT at all? Does anyone know a 99% sure answer?

Very true. Nothing much is known about LNC μarch (except it's brand new). Not even enough to speculate about it. Like you said, it is definitely an unknown as of now, contrary to most claims I've come across.

And I do believe it's a fundamentally different approach compared to RWC & GLC focusing squarely on power efficiency from ground up. I think it may turn out more like ARM (Apple) design rather than older x86 designs.

Edit: One persistent rumor that keeps coming up often is that LNC has foregone hyper-threading (probably lifting a page from Apple SoC). And it sounds a bit legit.

Edit: And i think it may top out at 3.5 to 4 GHz just like the Apple SoC.

 

[FlameTail]

And I do believe it's a fundamentally different approach compared to RWC & GLC focusing squarely on power efficiency from ground up. I think it may turn out more like ARM (Apple) design rather than older x86 designs.

Edit: One persistent rumor that keeps coming up often is that LNC has foregone hyper-threading (probably lifting a page from Apple SoC). And it sounds a bit legit.

Edit: And i think it may top out at 3.5 to 4 GHz just like the Apple SoC

Then there must be gigantic IPC gains to make up for the frequency loss.

 

[AMDK11]

In the case of LionCove, it is 99% certain that it will be more complicated than GoldenCove. That L1-I is 64KB 16-way, L1-D 48KB 12-way, L2 supposedly 3MB, L3 3MB and new instructions.

The lower pipeline and lower clock speeds mean that the IPC must be much higher than GoldenCove to achieve higher performance even at much lower clock speeds. Lower clock speeds mean lower power consumption, but also a sign that the core had to be significantly expanded.

My personal opinion is that if LionCove is truly a new approach and a clean sheet of paper, then beyond solid development, a lot of effort has gone into putting a lot of smarts into the core logic, rather than just loading resources to the brim. I hope that.

 

[FlameTail]

So if I remember right, Lion Cove was worked on by Jim Keller?

 

[adroc_thurston]

So if I remember right, Lion Cove was worked on by Jim Keller?

He wasn't doing anything CPU cores in general and IDC hated his guts in particular.
So no, absolutely not.

 

[controlflow]

Golden pig Upgrade posted a Cinebench power/efficiency curve with a new firmware. Depending on the firmware this might explain the differences between some tests. In another posting he says the latest Arc test driver improves low power gaming performance for the Arc tGPU, the driver is expected in 1 month.

Hopefully we will know soon if this is legit or bs.

If true, I'd consider the CPU portion of MTL as meeting expectations. I wonder if the retail units already have these updates.

 

[H433x0n]

He wasn't doing anything CPU cores in general and IDC hated his guts in particular.
So no, absolutely not.

Who is IDC?

 

[Markfw]

Who is IDC?

IDC USED to be a member called "Idontcare". But thats just a guess

Edit: see below. Most likely that instead of my guess.

 

[Khato]

Who is IDC?

In that context, most likely referring to Intel's Israel Design Center.

 

[Hulk]

In the case of LionCove, it is 99% certain that it will be more complicated than GoldenCove. That L1-I is 64KB 16-way, L1-D 48KB 12-way, L2 supposedly 3MB, L3 3MB and new instructions.

The lower pipeline and lower clock speeds mean that the IPC must be much higher than GoldenCove to achieve higher performance even at much lower clock speeds. Lower clock speeds mean lower power consumption, but also a sign that the core had to be significantly expanded.

My personal opinion is that if LionCove is truly a new approach and a clean sheet of paper, then beyond solid development, a lot of effort has gone into putting a lot of smarts into the core logic, rather than just loading resources to the brim. I hope that.

Now that Intel has moved to tiles the compartmentalization must be nice for both the engineers and managers. Meaning the CPU people need only really worry about the CPU tile, GPU people on that tile, I/O on theirs, and the SoC people bringing them all home (making the connections). Now that have a layout in Meteor that they know works. They just need to make that CPU tile better. Yeah, easily written, I know. If the clock speed regression from ARC to RPC is 10% then they'll need that in IPC right off the bat before we even start talking about gains. The positive side of this is if they can get Arrow Lake out the door at 5GHz and it is more performant in both ST and MT then they can start to play the "ramp up the clocks" again game. Or should I say "ramp up to keep up."

 

[Henry swagger]

Wild that people hate Intel so much that they create dedicated troll accounts.

Insane lol

 

[Geddagod]

In the case of LionCove, it is 99% certain that it will be more complicated than GoldenCove. That L1-I is 64KB 16-way, L1-D 48KB 12-way, L2 supposedly 3MB, L3 3MB and new instructions.

The lower pipeline and lower clock speeds mean that the IPC must be much higher than GoldenCove to achieve higher performance even at much lower clock speeds. Lower clock speeds mean lower power consumption, but also a sign that the core had to be significantly expanded.

My personal opinion is that if LionCove is truly a new approach and a clean sheet of paper, then beyond solid development, a lot of effort has gone into putting a lot of smarts into the core logic, rather than just loading resources to the brim. I hope that.

where's the L1 cache sizes from?
L2 is supposedly 3MB- but its split into two- prob a 2.5MB L2 and 0.5MB L 1.5. Apparently LNC adds another level of cache.

 

[majord]

It's fortunate for Intel AMD don't offer higher core counts on their APU's.. Even with a significant core and thread count (total - combined P and E cores) , they're STILL this far behind perf/watt. 12 core Phoenix parts (for arguments sake) would absolutely demolish MTL . Similar story for graphics it seems, though here it's also combined with the RAM bottleneck preventing either to really scale much higher performance there.

 

[Thunder 57]

Wild that people hate Intel so much that they create dedicated troll accounts.

Wild that people hate AMD so much they create websites like Userbenchmark.

 

[igor_kavinski]

The positive side of this is if they can get Arrow Lake out the door at 5GHz and it is more performant in both ST and MT then they can start to play the "ramp up the clocks" again game. Or should I say "ramp up to keep up."

i9-15900K is gonna have a pretty tough time trying to beat the upcoming i9-14900KS. I doubt that it will go higher than 5.5 GHz so it's gonna need some crazy IPC to level the playing field and then also need to have a pretty strong IMC to get the edge in MT workloads with higher speed DDR5. Forget beating AMD. Intel has enough of a challenge beating themselves.

 

[igor_kavinski]

IDC hated his guts in particular.

For telling them how to do their job, I suppose? Or more amusingly, he probably called them morons to their faces.

 

[H433x0n]

i9-15900K is gonna have a pretty tough time trying to beat the upcoming i9-14900KS. I doubt that it will go higher than 5.5 GHz so it's gonna need some crazy IPC to level the playing field and then also need to have a pretty strong IMC to get the edge in MT workloads with higher speed DDR5. Forget beating AMD. Intel has enough of a challenge beating themselves.

I mean, even Intel's own projections have it beating it (albeit by a measly margin). Their last proper core redesign netted them ~20% IPC and if they were to do that again they'd just need 5.0ghz boost clocks to roughly break even. I don't see it hitting 5.5ghz boost clocks, I think it'll probably top out at 4.8-5.2ghz depending on how well N3B does over the course of the next year.

Looked back at the ARL projections and tbh, they're not as bad as I remember. It's projected +10% on Geekbench, SysMark, CrossMark, Speedometer & WebXprt. IF it actually does that I suppose that's fine, those are the metrics that matter for your average user.

 

[controlflow]

The mediocre English speaking tech Youtubers should learn how to do a proper HW review from these guys

I can't understand it but the data goes way more in depth than the other reviews I've seen.

Would be nice if they can redo some of the power and battery tests with the new microcode update. If this data really is accurate, MTL looks pretty good especially when you consider the GPU and gaming benchmarks they also showed.