Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[invisible_city]

Lunar Lame? It is a huge advance in the power and system level department. Again, what are you smoking?

The power management advances and demonstrations back up Intel's claims of beating ARM/Apple on battery life!

Calm down it was a typo. If you can't tell I think Lunar Lake is great, I don't know what to tell you, focus on the details man

 

[Hitman928]

It's 140mm2 for the die size.

Yep, still getting over 4 mm^2 with a tool (~4.25 mm^2).

 

[invisible_city]

That has nothing to do with perf/clock.

The curve has shifted likely due to design/process change which benefits lower power.

I don't know what you're responding to. IPC absolutely shifts depending on where you are on the power curve, because power/frequency relationship is not the same at every point on the curve, meaning you have performance x1 and clock y1 and performance x2 at y2, but x1/y1 != x2/y2 by some function of x, y.

I wrote a response to the worry people have that Lion Cove < Turin. That may not be true, because 1) Intel was not speaking about the architecture Lion Cove, but rather the Lunar Lake implementation, 2) they chose to highlight IPC at Lunar Lake's specific (likely upper) power level.

edit: Even for example adding AVX 512, will suddenly make 14% jump, as will HT, as will .5MB more L2. And on mobile, that IPC benefit comes at greatly reduced power, better than Zen 5 at lower power, I expect. I'm not worried about Lion Cove competitiveness in server, or mobile, less sure about desktop.

 

[Hitman928]

Yep, still getting over 4 mm^2 with a tool (~4.25 mm^2).

I'm getting the E-cores at ~45% the size of the P-core (~1.93 mm^2) if I include 1/4 of the L2 cache.

 

[DavidC1]

Yep, still getting over 4 mm^2 with a tool (~4.25 mm^2).

Take the picture here:

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The total size is 537 x 439 which is 251,547 which = 140mm2
Skymont is 46x41 = 0.95-1.05mm2
Lion Cove is 72x76 = 2.95-3.05mm2.

It's without L2 for Skymont. For Lion Cove it's hard to tell what the L2 is, because it's more highly integrated into the core and one of the blocks in the rectangle.

 

[invisible_city]

Let's think of that die shot.
-Take out the P cores
-Take out the NPUs

There's probably enough room left to put a 20 Xe core monster in there. So much for "AI revolution". 20 Xe cores 320 EUs in old Intel terminology. Skymont is more than fast enough to feed such a GPU.

Yeah, I'm a bit worried about NPU focus as well.

Taking a step back though and thinking about the future of GPUs, it may make sense. Nvidia GPUs are basically SOCs now, with some small amount of real estate dedicated to rendering specific stuff, and a large number of matrix multiply units, called tensor cores. The GPUs are getting so large that now we have multiple logic dies. The next logical progression would be to disaggregate the tensor cores and rendering bits. You've now described an NPU + GPU. The question is when the fabric becomes fast enough for that to really be possible, so that the GPU can still make productive use of the NPU for "AI" rendering (e.g. XeSS).

 

[Hitman928]

Take the picture here:

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The total size is 537 x 439 which is 251,547 which = 140mm2
Skymont is 46x41 = 1.05mm2
Lion Cove is 72x76 = 3.05mm2.

It's without L2 for Skymont. For Lion Cove it's hard to tell what the L2 is, because it's more highly integrated into the core and one of the blocks in the rectangle.

Are you including the IO block and dummy block when estimating? Those aren't included in the 140 mm^2 area. . .

 

[invisible_city]

This matches what Exist has said for years, including that P Core tried to kill E core team and also others Cores projects at Intel. And that they were very adversarial against Jim Keller while the E core team was very helpful and accepted his guidance.

Maybe P core team is the last thing standing between Intel and greatness. I hope they adapt. If Intel allows themselves to be ruled by politics, they're not going to have a good time.

 

[DavidC1]

Are you including the IO block and dummy block when estimating? Those aren't included in the 140 mm^2 area. . .

Yup, you are right. I stand corrected.

 

[DavidC1]

Maybe P core team is the last thing standing between Intel and greatness. I hope they adapt. If Intel allows themselves to be ruled by politics, they're not going to have a good time.

This is always going to happen. Companies, groups, and countries rise and fall. Because they are made of living entities, and have all the goodness and badness of human beings.

One day we might see the E core team stagnate. Likely right after their absolute peak. And if Gelsinger is indeed a great CEO, that won't last either. He is already in his 60s.

Right now they still can do better - beat ARM.

 

[poke01]

Lunar Lame? It is a huge advance in the power and system level department. Again, what are you smoking?

The power management advances and demonstrations back up Intel's claims of beating ARM/Apple on battery life!

I don’t think Intel ever claimed it beat M3/M4 in battery life, if they did they would have mentioned it in the keynote.

But Pat did say Lunar got a better CPU, GPU, NPU than the X Elite. If Intel had beaten Apple in CPU and GPU, they would have shouted from the rooftops.

In 2023, they did claim performance per watt leadership in their slides with Lunar but Apple has also progressed since then.

The only saving grace for XElite, is that it ships this month. While Lunar is Q3.

 

[DavidC1]

In 2023, they did claim performance per watt leadership with Lunar but Apple has also progressed since then.

The only saving grace for XElite, is that it ships this month. While Lunar is Q3.

Sorry, I meant ARM in general. This is Windows 8 on ARM all over again. Bay Trail stopped WoA in it's tracks with it's 50% perf/clock gain.

They were talking about 20% lower power in Teams over Elite right? Watch it do that elsewhere.

Meteorlake had potential with the LP-E core but in reality it was useless and barely kept anything off of it. Skymont with the greatly improved uarch and doubled cores along with higher maximum frequency allows most of the applications to be on it. Also, unlike Meteorlake the thread director and power management actually works. They were talking about the new coordination allowing 35% reduction in Teams, meaning without it would have been 8% better for AMD, rather than 30% lower than them.

 

[invisible_city]

I don’t think Intel ever claimed it beat M3/M4 in battery life, if they did they would have mentioned it in the keynote.

But Pat did say Lunar got a better CPU, GPU, NPU than the X Elite. If Intel had beaten Apple in CPU and GPU, they would have shouted from the rooftops.

In 2023, they did claim performance per watt leadership in their slides with Lunar but Apple has also progressed since then.

The only saving grace for XElite, is that it ships this month. While Lunar is Q3.

I think Lunar Lake may be competitive with M3, depending on the power envelope and workload.

Snapdragon X Elite vs Intel Core Ultra and Apple M3: Qualcomm's SoC reportedly excels in efficiency and outperforms Meteor Lake

Qualcomm has finally compared the Snapdragon X Elite to the latest Intel Core Ultra and Apple M3 processors and the results look quite promising, at least for the lower power SKU. For instance, with a 23 W power limit, the Snapdragon X Elite beats the Apple M3 SoC, the Core Ultra 7 155H, and the...

www.notebookcheck.net

Performance per watt improvement of M3 Pro is 2x vs 155h or 185h, and ~3.5x for M3 (Air implementation) vs 155h.

Intel claims 3x PPW improvement for Skymont vs LP E cores. However, the 3.5x improvement for M3 Air vs 155h is on a heavy multithreaded workload, which means we're comparing a mixture of P + E cores, not LP. Skymont will be even more than 3x PPW vs E-Cores.

For workloads where Lion Cove is little used, which will be the majority for casual users (since now we won't schedule HT threads on Lion Cove, and E-cores take priority up to 4 threads), we may see very close to M3 (Air iteration) PPW. When Lion Cove is used a lot it will be of course much less impressive.

 

[Hitman928]

Yup, you are right. I stand corrected.

Glad we worked it out

Here's what I got in visual form (I'm including 1/4 the L2 area for the E-core):



P-cores are still pretty big. E-cores have definitely grown in area relative to the P-cores as well.

 

[invisible_city]

Glad we worked it out

Here's what I got in visual form (I'm including 1/4 the L2 area for the E-core):

View attachment 100585

P-cores are still pretty big. E-cores have definitely grown in area relative to the P-cores as well.

So Lion Cove is still quite a bit bigger than Zen 5, given process difference?

 

[DavidC1]

Intel claims 3x PPW improvement for Skymont vs LP E cores. However, the 3.5x improvement for M3 Air vs 155h is on a heavy multithreaded workload, which means we're comparing a mixture of P + E cores, not LP. Skymont will be even more than 3x PPW vs E-Cores.

I'm not confident if it can actually reach Apple's perf/watt. I wouldn't be surprised if the battery life can be matched, but that's different. The problem is even their E cores are still behind Apple in that department, and the 1/3 power they are quoting is in the most optimistic implementation.

By the way it looks like it's 40% reduction in power at the board level as well. We're potentially going to see another 50% jump in battery life as with Haswell.

 

[FlameTail]

Maybe P core team is the last thing standing between Intel and greatness. I hope they adapt. If Intel allows themselves to be ruled by politics, they're not going to have a good time.

P core team should be canned. E-core is the future!

 

[Hitman928]

So Lion Cove is still quite a bit bigger than Zen 5, given process difference?

For Zen 5 I get ~4.7 mm^2 when including L2. Assuming cache doesn't scale at all moving from N4 -> N3B and you got the advertised scaling for the rest of the core, then LNC would be somewhere around 10 - 15% bigger iso node. Those are big assumptions though (and the Zen 5 estimate is really rough given the quality of the image). Overall, Intel P-cores have improved in core area relative to Zen 5. It's possible that they've physically removed the full 512-bit widths from the LNC consumer cores though, that would help with area.

 

[gdansk]

P core team should be canned. E-core is the future!

If the P core is a complete mess as claimed and still they're managing to make improvements there must be some very smart people.
Not a good idea to fire people who can do that.

 

[invisible_city]

For Zen 5 I get ~4.7 mm^2 when including L2. Assuming cache doesn't scale at all moving from N4 -> N3B and you got the advertised scaling for the rest of the core, then LNC would be somewhere around 10 - 15% bigger iso node. Those are big assumptions though (and the Zen 5 estimate is really rough given the quality of the image). Overall, Intel P-cores have improved in core area relative to Zen 5. It's possible that they've physically removed the full 512-bit widths from the LNC consumer cores though, that would help with area.

So 10-15% bigger, and likely 10-15% better IPC (I think that RWC is ahead of Zen 4?). If so, that seems fine.

Edit: Actually if Lion Cove now is physically missing AVX-512, I would expect a bigger uplift, though again Zen 5 IPC numbers include some AVX 512 workloads, so comparison outside AVX 512 is not clear.

Edit2: Raptor Cove is only around 1-5% ahead of Zen 4 according to Spec 2017. Not sure what Zen 5 uplift is outside of AVX 512, so hard to compare to Lion Cove in lunar lake.

 

[Hitman928]

So 10-15% bigger, and likely 10-15% better IPC (I think that RWC is ahead of Zen 4?). If so, that seems fine.

I would say too early to call, but if we take AMD and Intel at their word for IPC increases, then AMD will be a little ahead (edit: and would be significantly ahead where AVX-512 is used but that is not used much in consumer apps at this point in time).

 

[invisible_city]

I would say too early to call, but if we take AMD and Intel at their word for IPC increases, then AMD will be a little ahead.

Yeah, I think this comes down to whether AVX 512 workloads are included in the IPC calculation or not.

 

[Wolverine2349]

This is always going to happen. Companies, groups, and countries rise and fall. Because they are made of living entities, and have all the goodness and badness of human beings.

One day we might see the E core team stagnate. Likely right after their absolute peak. And if Gelsinger is indeed a great CEO, that won't last either. He is already in his 60s.

Right now they still can do better - beat ARM.

Well yeah e-core team if they truly are progressing as good as this, should just replace the P core team and one unified core type again and bye bye hybrid arch and back to same type of core as only reason hybrid came about is because Intel P core team had cores too large and power hungry to get as many as AMD in a consumer sized socket at reasonable power draw and they needed the quantity of much weaker e-cores to be competitive in perfect parallel workloads with AMD. Otherwise Big.Little does not exist in desktop.

Conroe moment maybe in a few years and e-core team should replace P core team if things are truly progressing as rumored form e-core team?

 

[lightisgood]

So Lion Cove is still quite a bit bigger than Zen 5, given process difference?

Lion Cove has 8-way traditional decoder.
So, LNC's front-end is theoretically 1.75x bigger than GLC's.
LNC must not be smaller than Zen 5, isn't it?

 

[dullard]

I mean, you just gave a textbook justification of hybrid architecture. You didnt really address the point of my post though. Sorry to keep bringing up AMD in an Intel thread, but they are able to put 16 big cores into a chip and still have excellent performance and power consumption. I guess what I am trying to say, is that Lion Cove still seems behind in performance and/or power consumption, or they would not have to bother with the E cores. It is also disappointing that Lunar Lake and the most performant Arrow Lake are on a TSMC node. What happened to process leadership? I though 20A was supposed to bring leadership. Are we depending on 18A now? And if it is simply a matter of supply, I dont consider a process leading edge if it cant provide sufficient wafers with adequate yields to satisfy production demands.

With that rambling paragraph with no clear direction, and no attempt to actually address the conversation, it sounds more like you are just totally lost. So, I'll try again, at the beginning.

Every CPU core design has its own performance vs power curve. With no power, there is no performance. As you add more and more power, the potential performance goes up and up. But, it isn't linear. As you keep adding power, the relative gains in performance reach a point of diminishing returns. Where eventually you get very little performance gains for massive amounts of additional power. This curve gives designers and users multiple different ways to optimize things (maximize performance, maximize energy efficiency, some sweet spot in-between, etc).

Different core designs and different nodes have drastically different performance/power curves. TSMC's 5 nm node has way better curves than Intel's old nodes. So you are correct that the 7950X could fit 16 cores in and still be excellent. Sorry about an old image, but the image below is a great one to use for discussing this. Notice how the 3950X has more performance at every power level that it runs at than either Intel P or E core on that Alder Lake graph. That TSMC 5 nm node is great compared to Alder Lake's Intel 7 node.

Alder Lake’s Power Efficiency – A Complicated Picture

Reviews across the internet show Alder Lake getting very competitive performance with very high power consumption. For example, Anandtech measured 272 W of package power during a POV-Ray run. Our o…

chipsandcheese.com

But also look at the red curve, there are massive performance gains up to 11 W and very few gains past 11 W per core. Put 16 of those cores at 11 W each (176 W total) and you'd have a powerhouse. But, that 3950X chip is limited to ~125 W with 16 cores and doesn't normally run at that higher power level https://www.anandtech.com/show/15043/the-amd-ryzen-9-3950x-review-16-cores-on-7nm-with-pcie-40/2. At 125 W, each of the 16 cores only gets 7.8 W. Instead of a core doing ~28 MB/s of work each (theoretically ~28 * 16 = ~448 MB/s is possible), they are power limited to only achieve ~17 MB/s each (~272 MB/s). Had the chip only had 12 cores instead of 16, each of the 12 cores would get ~10.5 W of power ~25 MB/s, and do a total of ~300 MB/s of work. The extra 4 cores reduces performance because power must be spread thin.

As for Lunar Lake, scroll up a few posts to this graph:
As you add in more and more cores, each core gets less and less of the power. Suddenly you find you are on the left side of that graph. The E cores actually have MORE performance than the P cores when power limited. That is why they bother to have E cores.

If power wasn't a limitation, then you would be correct. Just flood as many P cores as you can, set them all to the highest power possible, and we'd have this great imaginary chip. But that ignores limitations of reality and compromises that must be made.