Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Bouowmx]

Confirm my understanding of the latest lakes?

Desktop:
2024-5: Arrow Lake 8+16, TSMC 3/Intel 20A
2025-6: Arrow Lake Refresh 8+32, same process?
2026-7: Nova Lake, Royal Core?

Mobile:
2024-5: Lunar Lake and Arrow Lake, TSMC 3/Intel 20A
2025-6: Panther Lake (covering Lunar Lake's segments as well), Intel 18A
2026-7: Nova Lake, Royal Core?

 

[Hitman928]

The comparison had it very clearly labelled. LNC vs SKT both with cache. And then LNC vs SKT both without cache. The first one was a bit rough due to some issues with the images i guess. The second one has better comparisons with hi res images and more accurate/revised results which put it at 1:3 exact (without cache for both).

I tried to locate it for a while without much success. But will keep trying...


Six cores are kinda okay-ish. But quad cores? Oh god!

If I compare the E-core without L2 cache to the P-core with L2 cache, I get appx. a 1:3 ratio (1.5 mm2 vs 4.25 mm2). That's the only way you can get to that ratio based upon the image shown previously.

 

[ondma]

Confirm my understanding of the latest lakes?

Desktop:
2024-5: Arrow Lake 8+16, TSMC 3/Intel 20A
2025-6: Arrow Lake Refresh 8+32, same process?
2026-7: Nova Lake, Royal Core?

Mobile:
2024-5: Lunar Lake and Arrow Lake, TSMC 3/Intel 20A
2025-6: Panther Lake (covering Lunar Lake's segments as well), Intel 18A
2026-7: Nova Lake, Royal Core?

Desktop?
My understanding is that Arrow Lake 8+16 is TSMC and 6+8 is 20A
Nor sure what ARL=R will bring, but I think 8+32 is no longer on the roadmap.
Not sure after that. Is Royal Core even still a thing? Keller has been gone for quite some time from intel. Seems that if there is going to be a Royal Core it should be coming before 2026. Given the non-spectacular gains in Lion Cove, Intel seems to desperately need it.

 

[SiliconFly]

It'd be interesting to see what that power delta is in "real world" usage scenarios. The e-cores should be solely engaged often enough that it seems like P-cores having HT wouldn't be a big issue. But I could be very wrong.



Does that mean that Arrow Lake-S will include those transistors?

Apparently, except me, many here are hoping ARL-S would actually include HT. Even I think it might have it cos the Intel P core designers kinda implied it. But I'm not a fan of HT. Good for servers, but bad for client. A vestigial appendage from a bygone era. Time to kill off HT completely in client ARL parts if you ask me.

 

[TwistedAndy]

Apparently, except me, many here are hoping ARL-S would actually include HT. Even I think it might have it cos the Intel P core designers kinda implied it. But I'm not a fan of HT. Good for servers, but bad for client. A vestigial appendage from a bygone era. Time to kill off HT completely in client ARL parts if you ask me.

In Lion Cove, Intel has changed the design approach from "Sea of Fubs" to the "Sea of Cells" and refactored the existing libraries:

It allows them to have a set of "knobs" to control which features will be physically presented in the silicon. In Lunar Lake, we will have the Lion Cove core without HT, AVX-512, and some other stuff.

But in ARL-S and, probably, ARL-H, we will have HT.

 

[vanplayer]

Not sure after that. Is Royal Core even still a thing? Keller has been gone for quite some time from intel. Seems that if there is going to be a Royal Core it should be coming before 2026. Given the non-spectacular gains in Lion Cove, Intel seems to desperately need it.

Confirm my understanding of the latest lakes?

Desktop:
2024-5: Arrow Lake 8+16, TSMC 3/Intel 20A
2025-6: Arrow Lake Refresh 8+32, same process?
2026-7: Nova Lake, Royal Core?

Mobile:
2024-5: Lunar Lake and Arrow Lake, TSMC 3/Intel 20A
2025-6: Panther Lake (covering Lunar Lake's segments as well), Intel 18A
2026-7: Nova Lake, Royal Core?

Royal core project has been shut down and reason is unknown.

 

[invisible_city]

Royal core project has been shut down and reason is unknown.

Where did you get hat from?

 

[SiliconFly]

Royal core project has been shut down and reason is unknown.

Royal core itself is a rumor mostly spread by mlid. Thank god the imaginary project got shuttered cos it existed only in our minds. Actually, there weren't any credible leaks regarding the same.

 

[Geddagod]

Royal core itself is a rumor mostly spread by mlid. Thank god the imaginary project got shuttered cos it existed only in our minds. Actually, there weren't any credible leaks regarding the same.

Xino definitely has, and I don't remember for sure, but I think Raichu might have mentioned it here or there before too.
Why would you be thanking god that RYC, even if it was an imaginary project, got shut down? This would be pretty bad news. You are always complaining about how LNC seems like a dead end and now you are saying you don't want a fresh new core?
About the veracity of Royal Core, or any " radical next gen core pathfinding" teams being canned... who knows. But all I'm saying is that it wouldn't be too surprising. Just a couple days ago on the Intel subreddit there was talk of layoffs happening in DCAI. I wouldn't be surprised if this effected more than just that team- and cuts were being planned or in action at various parts of the company as well.
Though obviously should be hoping this doesn't happen.

Nor sure what ARL=R will bring, but I think 8+32 is no longer on the roadmap.

Imagine development of that got scrapped in favor for the new rumored SOC tile with a better NPU. Another victim of the AI hype.

Not sure after that. Is Royal Core even still a thing? Keller has been gone for quite some time from intel. Seems that if there is going to be a Royal Core it should be coming before 2026. Given the non-spectacular gains in Lion Cove, Intel seems to desperately need it.

2026-7: Nova Lake, Royal Core?

I agree with the sentiment, but Raichu has alluded before, and hell even MLID commented on this, that Panther cove was supposed to be a major (as in standard new p core) ipc bump but got pushed back. Panther Lake will apparently use Cougar Cove, Nova Lake panther cove, and the gen after that may use RYC, is my best guess.

14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy.

It's not the IPC I'm disappointed in the most, but what the perf/watt gains look like from both companies.

You can even breadboard a really basic chip, and it is a lot of fun

Me pulling an all nighter and struggling in my digital logic class to build a basic hex to 7 segment display circuit on my breadboard
Also, side note, istg Intel Quartus actually hates me, whenever I'm on a time crunch and need to create a waveform simulation it just crashes lol

https://twitter.com/x/status/1799525678032838797

Skymont 4.5ghz to 5ghz clocks ?🤔..

TBF this perf/watt curve isn't very encouraging... maybe I am missing something.

he Lion Cove micro-op cache grew from 4,000 micro-ops in Redwood Cove to 5.250 in Lion Cove

Funny how this is still less than Zen 4

nd the OoO depth or instruction window was increased from 512 to 576 micro-ops.

Wonder why this didn't see a larger increase. IIRC, all other recent "major P-core updates" came with a much greater % ROB depth increase.

nd indeed the L2 online curve grows to 2.5MB on Lunar Lake and 3 MB on Arrow Lake

The power usage of these core private caches have to be insane. So much SRAM, running pretty fast... one has to wonder why Intel is buffing their core private caches so hard when you have AMD on the other hand staying with like 1MB of L2 per core lol.

I'm too pretty much convinced that MTL is more of a case study than a real product.

Nah

Hard to say. Panther Lake covers too many verticals unlike Lunar Lake. It'd be nice if it adopts LNL design, but it may not work well on higher core count parts like 8+16.

Only rumored to go up to 4+8+4

Thanks to IDC, RWC is horrible. An abomination if you ask me.

You have much too high standards. What makes you think RWC is that bad?

 

[Hulk]

Xino definitely has, and I don't remember for sure, but I think Raichu might have mentioned it here or there before too.
Why would you be thanking god that RYC, even if it was an imaginary project, got shut down? This would be pretty bad news. You are always complaining about how LNC seems like a dead end and now you are saying you don't want a fresh new core?
About the veracity of Royal Core, or any " radical next gen core pathfinding" teams being canned... who knows. But all I'm saying is that it wouldn't be too surprising. Just a couple days ago on the Intel subreddit there was talk of layoffs happening in DCAI. I wouldn't be surprised if this effected more than just that team- and cuts were being planned or in action at various parts of the company as well.
Though obviously should be hoping this doesn't happen.

Imagine development of that got scrapped in favor for the new rumored SOC tile with a better NPU. Another victim of the AI hype.



I agree with the sentiment, but Raichu has alluded before, and hell even MLID commented on this, that Panther cove was supposed to be a major (as in standard new p core) ipc bump but got pushed back. Panther Lake will apparently use Cougar Cove, Nova Lake panther cove, and the gen after that may use RYC, is my best guess.

It's not the IPC I'm disappointed in the most, but what the perf/watt gains look like from both companies.

Me pulling an all nighter and struggling in my digital logic class to build a basic hex to 7 segment display circuit on my breadboard
Also, side note, istg Intel Quartus actually hates me, whenever I'm on a time crunch and need to create a waveform simulation it just crashes lol

TBF this perf/watt curve isn't very encouraging... maybe I am missing something.

Funny how this is still less than Zen 4

Wonder why this didn't see a larger increase. IIRC, all other recent "major P-core updates" came with a much greater % ROB depth increase.

The power usage of these core private caches have to be insane. So much SRAM, running pretty fast... one has to wonder why Intel is buffing their core private caches so hard when you have AMD on the other hand staying with like 1MB of L2 per core lol.

Nah

Only rumored to go up to 4+8+4

You have much too high standards. What makes you think RWC is that bad?

Every micro architecture, no matter how well designed has bottlenecks. I would think that where some areas of the core aren't as improved as we might expect would be because they were less bottlenecked than other areas that received more attention. But of course at the end of the day Intel and only Intel has all of the answers and the simulations that point to why they did what they did.

 

[Ghostsonplanets]

My understanding is that Arrow Lake 8+16 is TSMC and 6+8 is 20A

6+8 is both TSMC and Intel.

Is Royal Core even still a thing?

Yes. Who knows if it will ever be released though. Intel Politics are sadly a thing.

 

[eek2121]

The Intel P core designer stated clearly that if the HT structures are physically present in LNC and enabled, it uses more power. Thats one of the key reasons, LNC doesn't include HT in LNC. I think in LNL, LNC doesn't even include the HT related transistors.

This is correct. People drastically overthink how much these chips are able to power down silicon. You can't power down 'part' of a core unless it is gated off in a way that allows you to do so. SMT has never been like this.

14% for Intel this gen, 16% for AMD. All of the internet "experts" aren't happy. They should take their collective genius and do a start up and send their P core tape out to TSMC and show AMD and Intel how to get +40% IPC they think is so easy to achieve after picking the fruit from these cores for 40+ years.

Both AMD and Intel's new designs are miraculous. They are the best x86 designs in the world. Many have tried, many have failed. Two remain.

Have you read/watched all of the info on the design of Lunar Lake? I'm still churning through it but it is extremely impressive to my small brain. The changes to LNL are quite extraordinary, the attention to detail, to eeking out every last percentage of power and performance. How all of these pieces forms a gestalt. I'm impressed unless it's all a big like akin to faking the lunar landing. You know all things "Lunar" are fake.

Massive changes to the P core. Wider, smarter, another cache level. Same with the E cores and a huge IPC increase. A new node. On package fast power efficient memory. Finer grained bins along with a machine learning capable Thread Director that includes containment zones. It's brilliant in concept. We'll see how Intel delivers it but demos so far have been impressive compared to MTL.

Meanwhile, AMD has not released as much info but they have been diligently working on their 16 "all P core" beast and managed to squeeze out another 16% (on average) IPC increase. Totally different philosophy. No E's. Still using SMT and 16 brutally power cores on a super efficient node.

What could be better for us as consumers? Two amazing choices. Each arriving at the same destination but taking different paths. I love it. Better than I could have hoped for from both manufacturers.

I guess I am a fan boy but not of the manufacturer but of the tech.

Say it with me (Intel themselves said it): Lion Cove in Lunar Lake is not representative of future iterations/versions.

Arrow Lake will be > 14% faster than Raptor Lake. Significantly more power efficient as well.

 

[Hulk]

Say it with me (Intel themselves said it): Lion Cove in Lunar Lake is not representative of future iterations/versions.

Arrow Lake will be > 14% faster than Raptor Lake. Significantly more power efficient as well.

Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL? Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.

 

[SiliconFly]

Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL?
Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Very much possible.

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.

Best case they might even add another 15% IPC. LNC in ARL isn't just an updated LNC in LNL. They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Also remember, LNC in LNL isn't allowed to stretch it's legs due to power/thermal constraints. Not so in case of ARL. Some free bonus there too.

We may just receive 2% to 3% IPC uplift (over LNC in LNL) like you said. Or we may end up with a massive 30% uplift. Who knows? We can only speculate until they say so.

 

[invisible_city]

Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL? Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.

I am guessing 2-3% benefit too, considering for all the issues LP E cores in meteor lake had, they were still only 5% average slower than regular E cores.

Lion Cove on meteor lake will have faster/higher power fabric, faster ring bus, more cache, at a minimum.

 

[eek2121]

Do you think Intel is implying that ARL Lion Cove will be significantly different from Lion Cove in LNL? Thus far the only thing I've read/heard (and I've read/heard a lot) is that HT could possibly be included in Lion Cove for ARL. Are you thinking they will make other significant architectural changes to the core?

Lion Cove gaining more than 5% IPC ST in ARL compared to LNL would be kind of far fetched as they is generally most we see from major cache and/or memory subsystem changes. Furthermore LNL is already starting with a memory subsystem much faster than previous mobile designs.

I could see ARL picking up 2 or 3% over LNL in the P cores perhaps. A larger increase in compute would be in MT if HT was added.

I'm having a hard time understanding how Intel would make changes so significant to Lion Cove that it's not representative to Lion Cove in LNL? Or I don't understand the word "representative," which I always thought meant of a like kind, or an example of a group of similar things.

What I think we'll get:
More,
Higher L1/L2 bandwidth,
SMT,
Higher clocks

How much faster Arrow Lake is will depend largely on any clock regressions. Note that current claims about clock regressions are rumors and nothing more. Single core clocks probably won't regress much, if at all since they aren't power limited to begin with (yes, even on Intel processors lol). All core clocks WILL likely dip unless the process makes up for it.

Very much possible.


Best case they might even add another 15% IPC. LNC in ARL isn't just an updated LNC in LNL. They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Also remember, LNC in LNL isn't allowed to stretch it's legs due to power/thermal constraints. Not so in case of ARL. Some free bonus there too.

We may just receive 2% to 3% IPC uplift (over LNC in LNL) like you said. Or we may end up with a massive 30% uplift. Who knows? We can only speculate until they say so.

I think we are likely to see a 15-20% single core uplift, depending on the workload, depending on whether clocks drop, and by how much. This is based on the changes I mentioned above. Multicore uplift should be significantly higher, possibly 40-50%, as Intel has massively improved their E-cores and power consumption should be driven down considerably via process improvement.

A lot of it is going to come down to those power numbers. Unless they change it (AGAIN), Intel is dropping power limits to be more competitive with AMD parts. I believe the quoted PL2 number for Arrow Lake was 177W. AMD is currently 230W for their power limit, but TDP is capped at 170W. In addition, the cores would normally need more power, though if they can release on Intel 20A/18A/TSMC N3* that should mitigate most of the power consumption, if not all of it. There are some perf/watt improvements in the architecture, however, that should help. Intel went over some of it during the Computex talks.

 

[Magio]

Hopefully the fact they're putting 4 P cores in a 15W (+2W memory) SKU speaks to improved power consumption characteristics for Lion Cove compared to prior P core designs from Intel. I don't expect all cores on LNL to be able to truly stretch their legs within that power limit of course, but if they can even function adequately not too far from it that would be a bigger gen-on-gen improvement than even the IPC gains from Skymont.

IPC is of course important but power consumption and thermals have been far more pressing issues in recent Intel designs.

 

[invisible_city]

One thing I don't really understand is the uArch Skymont vs uArch Raptor Cove comparison. 1.2x performance at equal power and 40% lower power at equal performance: does anyone know if they're controlling for process node? Because Intel also cites 20-80% PPW at low power for Skymon vs Lion Cove, and those are on the same node; since Lion Cove is more efficient than Raptor Cove, the advantage for skymont over raptor cove must be greater, unless they're discussing different power envelopes.

 

[H433x0n]

TBF this perf/watt curve isn't very encouraging... maybe I am missing something.

Why? If you stop at 5W in this graph it’s fine. Crestmont perf/watt curve is good, I don’t see a reason why it’d change dramatically in Skymont.

You have much too high standards. What makes you think RWC is that bad?

It probably isn’t.

 

[Geddagod]

Why? If you stop at 5W in this graph it’s fine. Crestmont perf/watt curve is good, I don’t see a reason why it’d change dramatically in Skymont.

Ye, you're right. I take that back. Didn't actually pay attention to the low end of that graph.

One thing I don't really understand is the uArch Skymont vs uArch Raptor Cove comparison. 1.2x performance at equal power and 40% lower power at equal performance: does anyone know if they're controlling for process node?

Doubt it.

Because Intel also cites 20-80% PPW at low power for Skymon vs Lion Cove, and those are on the same node; since Lion Cove is more efficient than Raptor Cove, the advantage for skymont over raptor cove must be greater, unless they're discussing different power envelopes.

Probably.

Best case they might even add another 15% IPC.

Bruh

LNC in ARL isn't just an updated LNC in LNL.

It is

They were working in parallel from the beginning. Those two might be entirely different beasts for all we know.

Bro....

Or we may end up with a massive 30% uplift. Who knows?

Lmao

 

[Geddagod]

LNC's 18% higher perf/watt (at the lower end of the perf/watt curve) would only put it barely higher than Zen 4...
Edit: credit goes to David Huang, on twitter

 

[Hulk]

One thing I don't really understand is the uArch Skymont vs uArch Raptor Cove comparison. 1.2x performance at equal power and 40% lower power at equal performance: does anyone know if they're controlling for process node? Because Intel also cites 20-80% PPW at low power for Skymon vs Lion Cove, and those are on the same node; since Lion Cove is more efficient than Raptor Cove, the advantage for skymont over raptor cove must be greater, unless they're discussing different power envelopes.

Lion Cove and Skymont have been engineered very specifically. From Intel rep. talk I have been transcribing. Parenthesis are notes to myself.

So one of the questions this morning is, “Hey your last gen you had two low power ecores and now there are four E cores?” That's true because these cores scale way down low where the low power island did in in Meteor Lake. So we cover that use case (extremely low power) and we've also doubled the core count versus last year's low power Island so now we can get the E core benefit too (better MT performance) and as you scale up in performance we get a lot more out of all of these cores computationally. That allows us to simplify the design, reduce the area of the die, and essentially collapse two features (low, low power, and low power high performance) into one because these are simply more capable. If we look at them together, one thing I want to highlight here is that these cores are designed to cover a full range of power and frequency.



We do what we call what I call bottom up scheduling so the E core is first in scheduling, We want workloads to go to the most efficient core first, and then when the workload is too significant for that four core cluster to handle, only then do we move it upwards into the P core. But remember we do have Thread Director, we have intelligence scheduling technology so yes it is absolutely possible to jump straight to the P core first.



At the low end (of the power spectrum) the E cores are actually somewhere between 20 and 80% more performant (at iso power) than the P core, and at the high end kind of the opposite is true. You get 50 plus percent more performance out of the P core versus the E core. So this (full power/performance) range is why we do P cores and E cores (The E cores have a better performance/power ratio at low power and the P cores have a better performance/power ratio at high power). This range is why you can remove technologies like SMT, which have been around for forever, because now we have core technologies that can bring that single thread and multi-thread performance that was previously only deliverable through a technology like hyperthreading.

 

[Khato]

Yes. Who knows if it will ever be released though. Intel Politics are sadly a thing.

So very true. The royal core concepts and projections were quite intriguing, but also quite possibly in the realm of too good to be true. We'll just have to see how the LNC -> CGC -> PNC -> GFC P-core progression turns out.

 

[SiliconFly]

Bruh

It is

Bro....

Lmao

We'll see!

 

[invisible_city]

Lion Cove and Skymont have been engineered very specifically. From Intel rep. talk I have been transcribing. Parenthesis are notes to myself.

So one of the questions this morning is, “Hey your last gen you had two low power ecores and now there are four E cores?” That's true because these cores scale way down low where the low power island did in in Meteor Lake. So we cover that use case (extremely low power) and we've also doubled the core count versus last year's low power Island so now we can get the E core benefit too (better MT performance) and as you scale up in performance we get a lot more out of all of these cores computationally. That allows us to simplify the design, reduce the area of the die, and essentially collapse two features (low, low power, and low power high performance) into one because these are simply more capable. If we look at them together, one thing I want to highlight here is that these cores are designed to cover a full range of power and frequency.



We do what we call what I call bottom up scheduling so the E core is first in scheduling, We want workloads to go to the most efficient core first, and then when the workload is too significant for that four core cluster to handle, only then do we move it upwards into the P core. But remember we do have Thread Director, we have intelligence scheduling technology so yes it is absolutely possible to jump straight to the P core first.



At the low end (of the power spectrum) the E cores are actually somewhere between 20 and 80% more performant (at iso power) than the P core, and at the high end kind of the opposite is true. You get 50 plus percent more performance out of the P core versus the E core. So this (full power/performance) range is why we do P cores and E cores (The E cores have a better performance/power ratio at low power and the P cores have a better performance/power ratio at high power). This range is why you can remove technologies like SMT, which have been around for forever, because now we have core technologies that can bring that single thread and multi-thread performance that was previously only deliverable through a technology like hyperthreading.

Nice thanks