Question Intel Mont thread

[igor_kavinski]

https://store.acer.com/en-us/aspire-3-laptop-a315-510p-3905

First Gracemont laptop available for sale.

Anybody got disposable $500 to buy and test this laptop?

 

[igor_kavinski]

Good post about the monts: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41221152

 

[nicalandia]

Intel Sierra Forest 2P Cinebench Scores

https://twitter.com/x/status/1796637806686834752

 

[DavidC1]

Skymont is a killer core:
-9 wide decode, up from 6-wide from Crestmont using 3x3 cluster configuration, up from 2x3
-New innovation: Nanocode, Using "Nanocode" adds further microcode parallelism within each decode cluster.
-Increased uop queue capacity from 64 to 96
-8-wide allocate, up from 6
-16-wide retire, from 8
-Dependency breaking to reduce instruction latency
-416 ROB, up from 256
-Bigger, PRF, reservation stations, and L/S buffers
-26 dispatch ports, up from 17 on Gracemont
-Literal doubling of FP capability with 4x128-bit FMA units, versus 2 before.
-Doubled L2 bandwidth to 128 bytes per cycle

All the way offering 3:1 area advantage, and some power advantage over Lion Cove, the latest P core.

 

[trivik12]

i wonder why didn't Intel use Skymont for SRF. its release window was very close to Skymont release window.

 

[DavidC1]

i wonder why didn't Intel use Skymont for SRF. its release window was very close to Skymont release window.

It would have delayed the release further and it's a risk they shouldn't take since they want to recover the time lag from competitors. And that also delays their 5Y4N plans, which will be bad.

Servers also need extra validation. Worry not though, Clearwater Forest uses the latest E core, the Skymont-based Darkmont.

 

[DavidC1]

Skymont improvements continued...
-Shorter FMUL, FADD, FMA latency
-3 loads, up from 2
-4 STA from 2
-4192 from 3092 shared TLB
-L1 to L1 transfer bandwidth improved

In... novation!!

Skymont also now employs nanocode to enable parallel microcode generation to allow the three decode clusters to execute in parallel more frequently.

 

[Mahboi]

All the way offering 3:1 area advantage, and some power advantage over Lion Cove, the latest P core.

Have we started having returns on the power draw of Skymont?
We say E-core, but considering the extra things, it could be a lot less E than it used to be, or very close. I'm curious to see details. If Intel hasn't mentioned power draw yet, I expect it's quite a bit worse.

 

[NTMBK]

Have we started having returns on the power draw of Skymont?
We say E-core, but considering the extra things, it could be a lot less E than it used to be, or very close. I'm curious to see details. If Intel hasn't mentioned power draw yet, I expect it's quite a bit worse.

Depends on whether the E stands for power efficiency or area efficiency. Intel seem keen on reducing die size for some reason, now they have to pay TSMC for the wafers...

 

[Khato]

You can also think of SRF as somewhat of a proof of concept product. It's leveraging as much as possible from GNR and keeping core changes to a minimum. Which would be part of the reason why it ended up leap-frogging GNR and coming to market first. All the better for Intel as it's probably the better product for the majority of server volume.

Regarding Skymont efficiency - slide decks have plenty of performance versus power curves. It's better than Crestmont.

 

[DavidC1]

Have we started having returns on the power draw of Skymont?
We say E-core, but considering the extra things, it could be a lot less E than it used to be, or very close. I'm curious to see details. If Intel hasn't mentioned power draw yet, I expect it's quite a bit worse.

The process and design of the silicon their chips are on is optimized for frequency, thus is not completely optimal for the E core. The curve is flatter for faster clocked designs, thus take less power to reach for the designs that are capable of doing it. However the E cores stop before the P cores do, and voltage requirements increase dramatically towards the end.

In the optimized range, they are indeed much more efficient. Also, just being 12% off their P core performance per clock means it won't take a lot for Skymont to be more power efficient than Lion Cove.

Nevermind the humongous area advantage.

 

[Mahboi]

The process and design of the silicon their chips are on is optimized for frequency, thus is not completely optimal for the E core. The curve is flatter for faster clocked designs, thus take less power to reach for the designs that are capable of doing it. However the E cores stop before the P cores do, and voltage requirements increase dramatically towards the end.

In the optimized range, they are indeed much more efficient. Also, just being 12% off their P core performance per clock means it won't take a lot for Skymont to be more power efficient than Lion Cove.

I never had any doubt about that just from the area.
But I'm curious if this is an E-core in the traditional sense anymore.
Are we going to see a switcheroo where AMD makes a Zen 5 LP core while riding the success of mainline Zen 5, while Intel is taking their E-cores to become their performance cores and their LP cores replace them as E-cores?
(and will Pat burn the Israel Design Center?)

 

[trivik12]

its 140mm N3B die. That is not bad considering it houses everything except SOC die.

 

[gdansk]

its 140mm N3B die. That is not bad considering it houses everything except SOC die.

I think that's very good. It did not miss on density either.
But I wonder how much it costs to make

 

[invisible_city]

I think that's very good. It did not miss on density either.
But I wonder how much it costs to make

In one sense nothing since Swann prepurchased a lot of capacity. Sunk cost

 

[trivik12]

Sierra forest showing huge improvements in efficiency and that is with Crestmont plus core. Clear Water Forest will be a serious product that could target even more data center segments. That plus Panther Lake housing enhanced Skymont(Darkmont) on Intel 18A with Ribbon Fet/Power Via tech. That would show comps between Lunar Lake/Panther Lake very interesting. How would Intel 18A compare to TSMC N3B. Of course we will also see Arrow Lake Refresh on N3P?

 

[TwistedAndy]

Have we started having returns on the power draw of Skymont?
We say E-core, but considering the extra things, it could be a lot less E than it used to be, or very close. I'm curious to see details. If Intel hasn't mentioned power draw yet, I expect it's quite a bit worse.

Yes, we have a slide covering the performance and power curves. I think Skymont will work great on lower power levels (1-5W per core), but Intel may decide to push it to 4-5GHz in the desktop Arrow Lake. Unfortunately, the right part of Skymont was not shown on the chart.

In general, Skymont can be renamed to Conroemont

 

[Mahboi]

Intel Xeon 6780E / Xeon 6766E 144-Core Performance Benchmarks Review - Phoronix

www.phoronix.com

Phoronix benches out for SRF.

 

[invisible_city]

Yes, we have a slide covering the performance and power curves. I think Skymont will work great on lower power levels (1-5W per core), but Intel may decide to push it to 4-5GHz in the desktop Arrow Lake. Unfortunately, the right part of Skymont was not shown on the chart.

In general, Skymont can be renamed to Conroemont

Yeah leaks state 4.6ghz for Conroemont. I like the name

 

[TwistedAndy]

It may sound funny, but Conroemont (aka Skymont) is not that different from Apple Silicon P-cores in terms of internal structure. 9-wide decode, 8-wide allocation, 3 load units, 4 STA, 416 ROB...

Yes, it's not correct to compare CPUs this way, and a lot of details are simply missing, but still, it's not that different.

 

[gdansk]

But with 25% lower IPC?

 

[TwistedAndy]

But with 25% lower IPC?

The problem with IPC is that it heavily depends on the test suite. And Geekbench 6.3 is not the best one for comparing different platforms. Actually, in some cases, you can't compare results within one platform (SME).

The only viable metric is the actual performance of the apps you're using on the fixed power limit.

 

[DavidC1]

But with 25% lower IPC?

The M4 also has an advantage of having 9 stage pipeline compared to 14 for Intel's E cores. That alone is responsible for anywhere from 10 to 20% difference in performance assuming everything else is the same.

 

[gdansk]

The M4 also has an advantage of having 9 stage pipeline compared to 14 for Intel's E cores. That alone is responsible for anywhere from 10 to 20% difference in performance assuming everything else is the same.

But Skymont doesn't clock much higher with those extra stages. What are they doing in the extra stages? Decode?
I'm not finding good information anywhere.

 

[DavidC1]

But Skymont doesn't clock much higher with those extra stages. What are they doing in the extra stages? Decode?
I'm not finding good information anywhere.

There's obviously more than just pipeline stages. Itanium went from 800MHz, 10 stages to 1GHz, 8 stages on the same process technology, because the circuit design improved drastically with the coordinated and experienced HP engineers.

Or the fact that Athlon mostly matched Pentium III's clockspeed despite some deficiency in pipelines as well and facing against Intel's much superior process.

Another example is when Nvidia greatly increased clock speeds with the Pascal generation and mentioned improved circuit design. Circuit design also affects many other details such as instruction latency of the execution units.

Additional unknown are things like the branch predictor, and unknown other features in Apple's chip that is brought on by hard work and inspiration, not what has been done previously and is basically a copy of it.

Why do some companies make better cars than others? Why are some people smarter? Same question.

I'd love to see how they do with Darkmont and Arctic Wolf, if they can bring themselves to be a class-leading core and rivals Apple chips of that time in every area. After all, they started from the absolutely anemic Bonnell Atom.

 

[DavidC1]

The M4 also has an advantage of having 9 stage pipeline compared to 14 for Intel's E cores. That alone is responsible for anywhere from 10 to 20% difference in performance assuming everything else is the same.

By the way, this is the number Intel quoted back in the Netburst days. "Each additional pipeline stage is responsible for roughly 2-4% impact in performance".

We know from high pipeline CPUs that the cost of higher pipeline stages are greater than branch misprediction itself. Pentium 4 required greatly more transistors. Prescott had to balloon again. The extra transistors cost in terms of die size and power. There are likely other unknowns.

This is because prediction isn't perfect(it will never be). So while adding capabilities for better prediction is difficult and costly, in addition to the benefit being some of the time, addition of extra stages is a guarantee loss of performance.