It doesn't rule out the possibility of happening.
But its extremely unlikely. L2 cache is part of the core. They'd have to change the layout of the entire core to accomodate the doubled L2 cache, unless its physical array is 512KB in size and half is disabled already. Then they'd have to worry about keeping latency the same and power in control.
Even less likely because Servers and Mobiles have one thing in common: Power efficiency is a great boon to both. If they cut down associativity on client to lower power do you think they won't do that on server but rather turn around, keep the associativity the same and DOUBLE the size? You think they'd go with increased power, significant change in core layout and entirely seperate validation on the core for that?
Remember the expression "look at the forest not the trees"? Lowering power(like with reduced L2 associativity) to allow more multi-threading abilities on server, is just that. These kind of speculations just reduce the credibility of those saying them(referring to David Kanter).
Why do you think that doubled L2 would result in "significantly better" IPC? And what is "significantly better"? 5%? Because that's what "significant" means in CPU design. Likely it won't even net 3%, on modern architectures where caches have multiple tiers optimized for every code category, with L1 and L2 being very fast, but small ones. If the doubled L2 cache increases latency even by a little bit, then you'd lose most of the advantages of doubled capacity, because the point of L2 is fast access. L3 cache is a different story.
In fact, on servers if that increase in IPC means power use per core increases so much that you have to cut down on few cores, then they wouldn't use that IPC increasing feature.