And also: why doesn't CFL have Gen10?
When is Intel going to phase out production of SKL CPUs... or do you think that they have done so already?
Last order date is December 26, 2014
Last shipment date is June 5, 2015
Segmentation based on instructions is simply stupid. It creates fragmentation and by not making all instructions available on all CPU you just make sure that many developers will never use them because they don't have time and resources to develop multiple code paths. Chicken and egg problem.AVX is not much use, HT is much better. There is a 20-25% boost for many applications, it helps dualcore CPUs more than Quadcore CPUs. Basically in all games nowadays. AVX use cases are very limited for consumer. X264 and even more x265 benefits from it but not with 20-25%.
Segmentation based on instructions is simply stupid. It creates fragmentation and by not making all instructions available on all CPU you just make sure that many developers will never use them because they don't have time and resources to develop multiple code paths. Chicken and egg problem.
But I agree with you that HT is likely more useful for dual cores, my previous post was more about self-derision. I want my AVX-512
Fairly positive AVX-512 is confirmed for Cannonlake via compiler patches.AVX-512 won't find its way onto mainstream desktop CPUs for a long time, IMO. Certainly not at least until Icelake, but I would wager that even then AVX-512 will be kept off the client stuff.
Devs that want AVX-256 could not care less what people buying under $100 CPUs have.Segmentation based on instructions is simply stupid. It creates fragmentation and by not making all instructions available on all CPU you just make sure that many developers will never use them because they don't have time and resources to develop multiple code paths. Chicken and egg problem.
But I agree with you that HT is likely more useful for dual cores, my previous post was more about self-derision. I want my AVX-512
Fairly positive AVX-512 is confirmed for Cannonlake via compiler patches.
Yeah, they want to be sure their software will never run on a significant part of the marketDevs that want AVX-256 could not care less what people buying under $100 CPUs have.
Yeah, they want to be sure their software will never run on a significant part of the market
High performance laptops as well as desktops will not get Cannon Lake it seems, they will get Coffee Lake which is Kaby Lake which is Skylake. And even if CNL 2+2 has AVX-512 on the die, no way it's going to be enabled for 2-in-1 convertibles and thin laptops.
So CFL isn't based on CNL (e.g. no FIVR)? I haven't been paying attention recently.
AVX 2 has interesting uses many people are not aware of. Most think it's only about transcoding (which is a valid use even on Celeron and Pentium). But it's useful in 3d drivers, software rendering (think of small bunch of data not worth transfering to GPU, or accurate emulators), string operations (which are used everywhere).I don't think the kinds of people who buy Celeron/Pentium chips are going to be the kinds of folks who run software that could take advantage of AVX2.
Really, these advanced SIMD features are put in there primarily for workstation/HPC/datacenter customers, and they are not buying any CPUs without AVX2 these days. Soon, they won't be buying anything without AVX-512
There is only 1 thing that does not work out: there is still no evidence to it being a 32 core part from what i see.
Plus, there is something inherently wrong with jumping 8 cores up in a single gen, if you ask me.
There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.There is also no evidence that it's a 28C part.
HSW-EP to BDW-EP was a node shrink, however. These generally land a large improvement (compare Westmere-EX to IVB-EX).Same increase.
There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.
HSW-EP to BDW-EP was a node shrink, however. These generally land a large improvement (compare Westmere-EX to IVB-EX).
On same node we only had a 15C->18C jump (IVB HCC to HSW HCC). Not to mention, 2 more memory channels and few more PCI-E lanes.
10 core Westmere-EX did exist on 32nm, so if 32 cores are real, it is same scaling as Westmere-EX to HSW-EXEnd of 32nm -> 8 core SNB-EP
Of course it is, but the only evidence we have of it are Chinese bootleggers claiming it does.I think 32 cores is perfectly plausible.
10 core Westmere-EX did exist on 32nm, so if 32 cores are real, it is same scaling as Westmere-EX to HSW-EX
Of course it is, but the only evidence we have of it are Chinese bootleggers claiming it does.
There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.
ComputerBase @ Translate said:Already at the events in the summer like IDF 2016 and Hot Chips ComputerBase had repeatedly received the information that the Skylake server has not only 28 but 32 cores. What is now reported as direct "AMD Zen counter" by Intel
Iris Pro lives through Xeon. Too bad it's BGA, a LGA version of this SKU could have replaced Broadwell-C for desktops.
Xeon E3-1585 v5 (65W TDP) with Iris Pro P580
www.ark-pc.co.jp/i/12102517
There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.
HSW-EP to BDW-EP was a node shrink, however. These generally land a large improvement (compare Westmere-EX to IVB-EX).
On same node we only had a 15C->18C jump (IVB HCC to HSW HCC). Not to mention, 2 more memory channels and few more PCI-E lanes.
Nope, but 28C is the largest core count on samples shipped earlier. Now, if it is indeed 32C, great. But so far the only evidence i see is hearsay and Chinese folks claiming that.Makes no sense. Do you have evidence that Xeon E5-2699 V5 is a 28 core SKU? I bet you don't, means your evidence is meaningless. It is a native 32 core Die according to Computerbase, based on informations they received from events like IDF or Hotchips, they are saying that a bigger SKU than 28C was no surprise behind closed doors. Now think twice.
Considering that Skylake XCC has more PCI-E lanes, another interconnect, 2 more memory channels, having 8 more cores on top of that would presumably increase the die size way beyond land of reason. I mean, replacing a DDR3 controller with DDR4 one and adding 3 more cores added a whole 120mm^2 of die size. I would imagine adding 8 more cores would add similar amount of die size. And then we have MOAR uncore to work with.You don't see "Tick" chips with 6xxmm2 die size. It's always for the "Tock" chips. In that sense, 14nm has quite a bit of room to go considering Broadwell EP is 456mm2. Haswell EP was 660mm2. In contrast, Ivy Bridge was rather large at 541mm2. The growth on 14nm comes with Skylake. 6xxmm2 sizes were traditionally reserved for Itanium and Xeon Phi chips, but they weren't on a bleeding edge process either.