Intel Skylake / Kaby Lake

Page 37 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
136
That die is much more square than the HSW/BDW chips. Wonder what this means for SKL system architecture.

Well, 15W 2+3e is planned for Skylake. That must mean they changed the die floorplan and it results in a square die.

As for the small rectangular one it must be the 22nm PCH. It's far smaller than current ones. I wonder if that 22nm PCH also has the 64MB eDRAM.
 
Mar 10, 2006
11,715
2,012
126
Well, 15W 2+3e is planned for Skylake. That must mean they changed the die floorplan and it results in a square die.

As for the small rectangular one it must be the 22nm PCH. It's far smaller than current ones. I wonder if that 22nm PCH also has the 64MB eDRAM.

I don't think the PCH has the eDRAM; it's too small for that.
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
136
I don't think the PCH has the eDRAM; it's too small for that.

That is real strange. The rectangular die is too small for it to be a main chip since its on the same process(and ~50mm2), while the square one is too big to be a PCH(~90mm2). Remember also that the PCH gets a shrink to 22nm.

If we assume square one is the main chip, there has to be a reason they changed the shape. Same with the PCH if its the rectangular one.

2+3 dies are extremely long for a reason: http://media.idownloadblog.com/wp-content/uploads/2015/01/Intel-Broadwell-U-Iris-6100-image-001.jpg

If the rectangular one is not the 2+3 one, I assumed that its similar to how 4+3e dies are, and the requirement of interface for the eDRAM allows it to be rectangular.

Just my thoughts.
 

coercitiv

Diamond Member
Jan 24, 2014
6,400
12,857
136
Aren't Skylake U and Y supposed to integrate the PCH into the main die? That would mean the small chip is the eDRAM.
 
Reactions: Drazick

SAAA

Senior member
May 14, 2014
541
126
116
Aren't Skylake U and Y supposed to integrate the PCH into the main die? That would mean the small chip is the eDRAM.

I was thinking the same, they are still using 22nm for Broadwell's eDRAM but when Skylake-U/M launches it should be less expensive to port them on 14nm.

Any guess on the floorplan of the chip?
 

SAAA

Senior member
May 14, 2014
541
126
116
That's weird then: pixel counting (USB on the left as reference) shows around 87mm2 for the upper die and 45mm2 for the lower one.
So the CPU is barely larger than Broadwell dual core die and the PCH is... that small?

BTW my speculation on GT4 Skylake:



The die size is about 250mm2 and the eDRAM around 40, plausible for the shrink (the L3 in Broadwell more than halved in size from Haswell so L4 could do the same probably).
 

JTsyo

Lifer
Nov 18, 2007
11,774
919
126
Was ComputeX too early for Intel to talk about Skylake? If it's coming out in Aug, I was expecting some info from them. Will we not get anything official until actual release?
 

Sweepr

Diamond Member
May 12, 2006
5,148
1,142
131
Was ComputeX too early for Intel to talk about Skylake? If it's coming out in Aug, I was expecting some info from them. Will we not get anything official until actual release?

They mentioned it briefly and showed the Panther Mountain Skylake-Y tablet reference design.
Intel will fully unveil (and launch) Skylake in August at IDF San Francisco.

Hopefully there will be some interesting leaks in the next 2 months.
 
Reactions: Drazick

Dave2150

Senior member
Jan 20, 2015
639
178
116
Does anyone know if the DMI 3.0 link from CPU to PCH will still be limited to x4 lanes?

As I understand it, Z170 features 20 PCI-E V3 lanes - though what is the point in this, if the link from PCH to CPU is only x4?

I assumed I could have several PCI-E SSD's all running at max speeds with those 20 lanes - though if it's all going though a x4 link, won't it be severely limited?
 

ShintaiDK

Lifer
Apr 22, 2012
20,378
145
106
Does anyone know if the DMI 3.0 link from CPU to PCH will still be limited to x4 lanes?

As I understand it, Z170 features 20 PCI-E V3 lanes - though what is the point in this, if the link from PCH to CPU is only x4?

I assumed I could have several PCI-E SSD's all running at max speeds with those 20 lanes - though if it's all going though a x4 link, won't it be severely limited?

Its still 4 lanes, just upgraded in speed.

The extra lanes are only added to enhance the adoption of M2, nothing else. You would be limited to 2 M.2 SSDs at 2000GB/sec each.
 

BigDaveX

Senior member
Jun 12, 2014
440
216
116
That, and presumably making it easier to hook in external controller chips without compromising the PCIe slots or resorting to PLX chips.
 

Sweepr

Diamond Member
May 12, 2006
5,148
1,142
131

Nice find.
13.1% better performance from Core i7 6700K at stock (overall).
The integer scores are particularly impressive.

Core i7 6700K (up to 4.2GHz):
Multi-Media Integer 390,86Mpix/s (19% advantage)
Multi-Media Long-int 181,37Mpix/s (25.6% advantage)

Core i7 4790K (up to 4.4GHz)
Multi-Media Integer 328,08Mpix/s
Multi-Media Long-int 144,12Mpix/s

There's also per clock results in the individual results section.

Core i7 6700K: 79,73Mpix/s/GHz
Core i7 4790K: 67,42Mpix/s/GHz

18.25% better performance per clock.
 
Last edited:
Reactions: Drazick
sale-70-410-exam    | Exam-200-125-pdf    | we-sale-70-410-exam    | hot-sale-70-410-exam    | Latest-exam-700-603-Dumps    | Dumps-98-363-exams-date    | Certs-200-125-date    | Dumps-300-075-exams-date    | hot-sale-book-C8010-726-book    | Hot-Sale-200-310-Exam    | Exam-Description-200-310-dumps?    | hot-sale-book-200-125-book    | Latest-Updated-300-209-Exam    | Dumps-210-260-exams-date    | Download-200-125-Exam-PDF    | Exam-Description-300-101-dumps    | Certs-300-101-date    | Hot-Sale-300-075-Exam    | Latest-exam-200-125-Dumps    | Exam-Description-200-125-dumps    | Latest-Updated-300-075-Exam    | hot-sale-book-210-260-book    | Dumps-200-901-exams-date    | Certs-200-901-date    | Latest-exam-1Z0-062-Dumps    | Hot-Sale-1Z0-062-Exam    | Certs-CSSLP-date    | 100%-Pass-70-383-Exams    | Latest-JN0-360-real-exam-questions    | 100%-Pass-4A0-100-Real-Exam-Questions    | Dumps-300-135-exams-date    | Passed-200-105-Tech-Exams    | Latest-Updated-200-310-Exam    | Download-300-070-Exam-PDF    | Hot-Sale-JN0-360-Exam    | 100%-Pass-JN0-360-Exams    | 100%-Pass-JN0-360-Real-Exam-Questions    | Dumps-JN0-360-exams-date    | Exam-Description-1Z0-876-dumps    | Latest-exam-1Z0-876-Dumps    | Dumps-HPE0-Y53-exams-date    | 2017-Latest-HPE0-Y53-Exam    | 100%-Pass-HPE0-Y53-Real-Exam-Questions    | Pass-4A0-100-Exam    | Latest-4A0-100-Questions    | Dumps-98-365-exams-date    | 2017-Latest-98-365-Exam    | 100%-Pass-VCS-254-Exams    | 2017-Latest-VCS-273-Exam    | Dumps-200-355-exams-date    | 2017-Latest-300-320-Exam    | Pass-300-101-Exam    | 100%-Pass-300-115-Exams    |
http://www.portvapes.co.uk/    | http://www.portvapes.co.uk/    |