For example caches dont get bigger for free, you trade latency/power/area/size/associativity, end result is a different set of trade offs
I think the trade-off will be with frequency. I wouldn't expect it to be large though. Maybe 100-200MHz.
The latency isn't necessarily impacted. Across the
same design, going to a really large cache like on server has higher latency because the sheer size means it has to travel further. But on consumer designs, and especially with sizes as small as L2 its almost never true.
Core Duo had a 14 cycle latency L2 with 2MB size. Core 2 Duo had the same 14 cycle latency L2 but with double the size at 4MB. Interestingly Pentium M "Dothan" had lower latency at same 2MB indicating design decisions are much more important than physical size.* It's very possible the 1MB L2 might end up being 16-way with same latency as the 256KB 4-way one.
*Here the reasons are likely twofold. One to increase clock headroom and other because it moved to a shared cache between two cores.
I doubt that. I would say more, but then I would have to infract myself.
Haswell-E overclocks more than Broadwell-E and we know Broadwell chips have trouble reaching high frequencies. Just by that Skylake-X should clock higher. I think the 14nm+ benefits regarding max OC frequency will be negated by decisions to increase perf/clock for server designs though. Maybe it'll do 4.5. That's about the same as HSW-E. BDW-E was 4.2.
I'm sure CL will bring improvements.
I am not sure why people are expecting even 100MHz OC bumps for Coffeelake. It took saying "5GHz OC!!" 3 times before it became a reality. Even now, 7700K can't always do 5GHz. You are expecting a 6 core version to increase in frequency, when opposite will likely be true, even with 14++. The 12% gains are for much lower frequency models like laptops(will be running out of headroom soon) and servers.