Uhem, L3 cache is easily few times faster than RAM. Both on latency and bandwidth. Hell, L4 cache on Broadwell-DT was barely faster than DRAM, and even that was significant enough to matter.
Uhem, L3 cache is easily few times faster than RAM. Both on latency and bandwidth. Hell, L4 cache on Broadwell-DT was barely faster than DRAM, and even that was significant enough to matter.Level 3 cache is no better than RAM. And you really dont need an extra megabyte of RAM.
Unless Intel has significantly altered their cache model, the L3 cache is still inclusive. This means that everything that exists in L2 cache on a given core also has to exist in L3 cache - this means that for every 1 MB of L2 cache, there is only 1.375 MB of L3 cache.
Level 3 cache is no better than RAM
Question is, would Intel "burn" 1.05MB of L3 cache per core just to provide coherency?
SiSoftware entry for a Basin Falls CPU with 6C/12T (Skylake-X ES): http://ranker.sisoftware.net/show_r...d5e3daeadeeadbfd8fb282a4c1a499a98ffcc1f9&l=en
How do you figure from that result?Pretty much confirms it doesn't have full speed AVX-512.
So if I am reading this correctly the Skylake now only has lets use the 7920x model only has 16.5 MB of unique cache between the L2 and L3 and the 6950x has 25MB of unique cache? So the hope here would be that the extra speed on the L2 make up for losing about 10MB worth of extra data total which in theory would mean more wasted cycles on refreshing the cache from memory?
That's the question. But also it's a big if. It depends if level 3 cache is inclusive which it has been forever in intel uArch and also in skylake and kaby lake. So it's highly unlikely this is different but entirely possible. inclusive means L3 cache contains all data from L2 caches. IMHO this is important if the OS moves threads from core to core. But with this new config there really isn't much space left in level 3. Strange.
nclusive L3$ benefit cache coherency performance between CPUs (or in the case of AMD, dice within an MCM package).
This effectively means that 72.7% of Skylake-X's L3 cache could be used for mirroring L2 cache, where Broadwell-E only used 10% of its L3 for mirroring L2 cache.
Does this mean cache will be slower? No. We need benchmarks.
Stop worrying about level 3 cache.
Level 3 cache is no better than RAM. And you really dont need an extra megabyte of RAM.
Inclusive L3$ benefit cache coherency performance between CPUs (or in the case of AMD, dice within an MCM package).
Raja Koduri, Senior Vice President and Chief Architect, Radeon Technologies Group worked at Apple and worked closely with Intel too. He probably played an important role in these negotiations.
It remains to be seen when it will be formally announced and when it will start affecting AMD’s bottom line. The cooperation and agreement will allow Intel to access AMD’s graphics Intellectual Properties and most things Radeonish.
AMD will weaken its position to fight Intel on in the integrated solutions, but licensing money should help overcome that issue. Despite that fact that these companies compete, they are close when it comes to graphics.
Of course, when we came to know the existence of the deal, we will dig much harder to get the many more details about potential new products and if the Radeon will get inside of the future Intel CPUs. Intel takes a lot of time to implement a new architecture.
Pretty much confirms it doesn't have full speed AVX-512.
How do you figure from that result?
I still can't see why AMD would want Intel to essentially be able to make APUs to compete with AMD APUs and with AMD low end GPUs.Kaby Lake-G rumors getting intense:
http://www.fudzilla.com/news/graphics/43663-intel-is-licensing-amd-graphics
They'll need something bigger than 149mm^2 if they are to fit 2MB L3/core.
I still can't see why AMD would want Intel to essentially be able to make APUs to compete with AMD APUs and with AMD low end GPUs.
If it's just for Apple, then it's hardly even news.If Apple wants a single MCM/single chip solution in place of discrete Polaris 11 + Intel CPU, then a product like Kaby Lake-G would make sense.
We know 6C/6T is 9MB L3, and unless die sizes are official, I'm not wrong - perhaps they are using a bigger die than 149mm^2 or the 149mm^2 figure was inaccurate to begin with.You were wrong on this. I've got some news and I can say Coffeelake 6/12 comes with 12 MB L3. Don't talk as a given fact next time without confirmation.
Also Coffeelake-S is going to support DDR4-2667, at least the 6C version. I'm not sure about the 4C version, it might support DDR4-2400 only, not sure.
It would be faster memory than KL or BW-E supports. Not everything is about RyZen...We know 6C/6T is 9MB L3, and unless die sizes are official, I'm not wrong - perhaps they are using a bigger die than 149mm^2 or the 149mm^2 figure was inaccurate to begin with.
What's so special about DDR4-2667 support? Ryzen supports DDR4-2667 in single-rank 2 DIMM configuration.
Every new generation has officially supported faster memory than the previous one in the past few years. What would have been surprising is if it didn't do so.It would be faster memory than KL or BW-E supports. Not everything is about RyZen...
I'm not sure that CL support of 2667 is accurate, though.
I have seen no bench leaks of a 6C12T part, which would presumably have 12mb of L3.
How this fits in with 1151, I don't know.
We know 6C/6T is 9MB L3, and unless die sizes are official, I'm not wrong - perhaps they are using a bigger die than 149mm^2 or the 149mm^2 figure was inaccurate to begin with.
What's so special about DDR4-2667 support? Ryzen supports DDR4-2667 in single-rank 2 DIMM configuration.
Fine. I'll correct myself when it's official.Bro, the 6C/12T CFL-S will have 12MB of L3$, not 9MB.
Except that this is still really just Skylake/Kabylake. It's not even close to a new generation. It's a 6C KL chip.Every new generation has officially supported faster memory than the previous one in the past few years. What would have been surprising is if it didn't do so.