Awesome,architecture deep dive and overclocking. Also Gen9. Both seem focused on low power and efficiency. Nothing for Atom. No Xeon Phi, but we'll probably hear more from that sooner.
There seems to be less in the ARC topics than I would have expected for a TOCK.
Skylake appears to be more of a Tick based on information we have today.
Skylake appears to be more of a Tick based on information we have today.
This tock microarchitecture was completely redesigned
There seems to be less in the ARC topics than I would have expected for a TOCK.
Awesome,architecture deep dive and overclocking. Also Gen9. Both seem focused on low power and efficiency. Nothing for Atom. No Xeon Phi, but we'll probably hear more from that sooner.
i3-6100U old: http://browser.primatelabs.com/geekbench3/2745990
i3-6100U new: http://browser.primatelabs.com/geekbench3/2796427
The ST scores are very close. The MT scores aren't. Are you sure the benchmark is to blame or was the user running some other heavy CPU process?Nice. That also shows Geekbench scores vary a lot, not exactly the best test to make perf/clock comparisons.
http://www.digitimes.com/news/a20150618PD203.htmlChipzilla 14nm Skylake processors and 100-series chipsets for desktops are expected to be unveiled in early August at Gamescom in Germany.
...According to one source, there will be three different versions of Skylake server processors: Skylake-EX, Skylake-EP and Skylake-F. All of them will work in Socket P0, which is a Land Grid Array type of socket. Different sources provide slightly different number of socket contacts. One source indicates that there will be 3467 contacts, whereas newer source vaguely says "about 3000 pins". Socket P0 package will be larger than the LGA2011-3 package. Its size will be either 76mm x 51mm or 76mm x 56mm.
All Skylake server processors will support DDR4 memory, UPI interface, DMI 3.0 and have 48-lanes of PCI-Express 3.0. The DDR4 controller will have 6 memory channels, and it will support up to 2 DDR4-2400 DIMMS per channel, or one DDR4-2666 DIMM per channel. The UPI links will support 9.6 and 10.4 GT/s data transfers. The UPI stands for Ultra Path Interconnect, and older sources used alternative name for it: KTI or Keizer Technology Interconnect. The UPI interface is expected to scale better than the Quick Path Interconnect. It has more bandwidth, and it also allows multiple requests per message, which improves its efficiency.
The Skylake-EX will scale to 2, 4 or 8 sockets. The EX processors will have 3 UPI links and will come with new RAS features, such as Instruction Retry, Advanced Error Detection and Correction and Adaptive Dual Device Data Correction. The microprocessors will have up to 165 Watt TDP.
The Skylake-EP will scale to 2 sockets, and will have 2 UPI links. Thermal Design power of low-power -EP products will range from 45 Watt to 80 Watt, and standard-power processors will have up to 145 Watt TDP. Workstation-class Skylake-EP SKUs will be rated at up to 160 Watt TDP.
The Skylake-F will incorporate one link of first generation Storm Lake Fabric. The Skylake-F will use Multi-Chip packaging, that will house two dies, a Skylake die and a Storm Lake die. In all other aspects, the Skylake-F will be identical to the Skylake-EP. [...]
Any benchmarks out yet? Will the upcoming i5 6600 br comparable to let's say an i7 4790 performance wise in multi threading even with the lack of hyper threading?
I still have to understand why Skylake is expected to be such a big launch considering that we have very little info about why it should be that in the first place. I'l recap:
1 - The DDR3 to DDR4 transition. For anyone that knows what happened with DDR to DDR2 and DDR2 to DDR3, the trasition is always a very lame period, since RAM performance would be similar to what was previously archivable, but the modules will cost more since they're new. Besides, we know that modern CPU performance isn't Memory Bandwidth crippled.
Desktop Skylake supposedly supports both RAM types, alas, I don't recall hearing about Motherboard makers lineup, since they should offer variants of many of their most popular models for each RAM type. Otherwise, building a new Skylake system with DDR4 would sustantially increase its price with no actual performance benefit.
2 - The fact that since I think Haswell (2 years ago), we don't have any architectural deep dive, which AnandTech used to do in great detail. We still don't have lots of details about Broadwell IPC improvements, much less why Skylake should be faster.
Remember, Haswell was a "tock", yet it provided a mere 5% or so higher IPC than Ivy Bridge, but lowered the max attainable Frequency (That is going backwards since Sandy Bridge). That Skylake is a "tock" means nothing after Haswell.
3 - The extremely bad precedent that Desktop Broadwell launch is setting. Even after more than 6 months of delay, there are still BIOS issues, like if Motherboards makers didn't had enough time to test it. I know that mass production was delayed, but no info regarding how much time the BIOS devs had Engineering Samples at hand to explain for the inmature BIOSes. That some overclockers are claiming BIOS issues during demos that should showcase how good it is with a handpicked sample, is rather alarming.
Broadwell itself was pretty much a paperlaunch, there is still null or limited retail availability. With such a recent precedent, are you expecting inmediate Skylake availability after launch, or what? This is going back to the 2000s when you had Intel launching products which you can't adquire for months to come. An August launch with who-knows-when retail availability isn't very promising.
And please, lets not talk about 14nm Frequency scalability. Broadwell seems to go backwards in that area compared to Devil's Canyon, which was rather unexpected, since supposedly with FinFET and the FIVR cost already paid for in Haswell, Broadwell should go back where a shrink means more Frequency. You need to have rather big hopes in the fact that a new architecture can increase BOTH IPC and Frequency headroom.
4 - Skylake seems to be highly focused in even more GPU performance. This means that there should be another big jump in Skylake IGP, maybe comparable to what Broadwell did over Haswell, while there is little to be said in the CPU area. This means that enthusiasts will keep going on complaining that now you have a massive percentage of the die size dedicated to the IGP while we're still using Quad Core Processors as the Desktop top range. It means that with info we have, it would be a great mainstream Processor but it wouldn't set a new high for CPU horsepower.
Did I miss anything about why Skylake has soo much fuzz about it?
You pretty much need an i7 6700(K) for that.
Sky Lake also supports HWP (HARDWARE-CONTROLLED PERFORMANCE STATE), but that feature seems to be already in Broadwell (Xeon-D)HDC forced idle operation can be thought of as operating at a lower effective frequency. The effective average frequency computed by software will include the impact of HDC forced idle.
The primary use of HDC is enable system software to manage low active workloads to increase the package level C6 residency. Additionally, HDC can lower the effective average frequency in case or power or thermal limitation.
Did I miss anything about why Skylake has soo much fuzz about it?
Hope for a full HEVC decoder like the GTX 960 has (aka not the hybrid junk Broadwell or a 750 ti has) with a complete Linux driver for VAAPI support.
That is what I want anyway.
Not really related since its Broadwell, but anyone noticed that there are two Core i5 5675C?Desktop Skylake launch models (Intel Product Change Notification): http://qdms.intel.com/dm/i.aspx/dabacf8e-2957-4fd9-9d22-899bd5fd1bca/PCN113879-00.pdf
We're getting closer and closer to launch.