Intel Skylake / Kaby Lake

[wildhorse2k]

Needless to say Intel will have to fix the memory latency, write memory performance and poor VRMark performance or many people could be put off from going into X299. Not to say competition product will be better.

 

[IntelUser2000]

Needless to say Intel will have to fix the memory latency, write memory performance and poor VRMark performance or many people could be put off from going into X299. Not to say competition product will be better.

It's possible it might not be, at least tiny improvements.

It's still a server-focused core. The improvements will be geared for that. There are areas where server and home usage are similar but also that are not.

Another possibility is that Skylake-X or Skylake-SP as a core is just not that great.

 

[JoeRambo]

https://www.researchgate.net/public..._for_flexible_and_efficient_cache_hierarchies
(credit RWT forum)

Intel seems to be doing some real smart things with LLC. While data is not inclusive, tags are. So that removes some of my fears about server CPUs suffering hard in thread communication.

And yeah, I'd not rush to conclusions. Simple BIOS or microcode revision to change snoop protocol or enable prefetch into L3 could result in performance differences.

 

[multippp]

Core i9-7900X final rock stable 4,7 GHz, 3 GHz unCore, 3733 MHz Quad mem-channel
Final, 24/7 Core i7-7900X settings ... 4,7 GHz at 1,25V. 3 Ghz unCore at "Auto", memclock 3733 MHz quad channel. Not bad i think
AIDA has no full support for X299, BCLK, CPU clock, MEM clock are not correct. Look at CPUz screen, there is all OK.

 

[IntelUser2000]

Intel seems to be doing some real smart things with LLC. While data is not inclusive, tags are. So that removes some of my fears about server CPUs suffering hard in thread communication.

That seems pretty nice. 4-10% gain compared to traditional inclusive hiearchy.

Though research paper doesn't necessarily mean it exists today. But the timing coincides well with Skylake-SP.

 

[JoeRambo]

Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?

But cache results are disappointing.

5Ghz Kaby has:

same L1 ( 0.8ns or 4 cyckes)
way much better L2 ( 2.4ns vs 4.6ns here, but could be fluke result as it is very sensitive to timing, 4.6ns is 20+ cycles???)
and L3 is sub 10ns for 4.X ghz uncore.

So yeah, I can see why some of the tests are suffering.

 

[mikk]

Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?

But cache results are disappointing.

5Ghz Kaby has:

same L1 ( 0.8ns or 4 cyckes)
way much better L2 ( 2.4ns vs 4.6ns here, but could be fluke result as it is very sensitive to timing, 4.6ns is 20+ cycles???)
and L3 is sub 10ns for 4.X ghz uncore.

So yeah, I can see why some of the tests are suffering.

Memory write seems a bit slow on this SKL-X compared to Broadwell-E:

https://d1rktuf34l9h2g.cloudfront.net/5/5b/5b83c75c_69aida.png


But the main issue is clearly L2 and L3 latency. SKL-X with a higher core clock is slower there, not good. Much smaller L3 and on top of that latency is worse with the new cache structure. No wonder that in some benchmarks IPC is down. The only hope is that the Bios isn't fully optimized for SKL-X yet.

 

[TheF34RChannel]

Core i9-7900X final rock stable 4,7 GHz, 3 GHz unCore, 3733 MHz Quad mem-channel
Final, 24/7 Core i7-7900X settings ... 4,7 GHz at 1,25V. 3 Ghz unCore at "Auto", memclock 3733 MHz quad channel. Not bad i think
AIDA has no full support for X299, BCLK, CPU clock, MEM clock are not correct. Look at CPUz screen, there is all OK

He's not showing some of the important things in CPU-Z, like speed, no temp info, no results so I find the video quite pointless.

 

[multippp]

[RUMOR] Intel will release Skylake-X SKUs with soldered IHS in the near future
According to our sources, Intel could release in the near future (4Q17 or 1Q18) the Skylake-X SKUs with soldered IHS.

source - http://www.bitsandchips.it/52-engli...e-x-skus-with-soldered-ihs-in-the-near-future

 

[TheF34RChannel]

[RUMOR] Intel will release Skylake-X SKUs with soldered IHS in the near future
According to our sources, Intel could* release in the near future (4Q17 or 1Q18) the Skylake-X SKUs with soldered IHS.

source - http://www.bitsandchips.it/52-engli...e-x-skus-with-soldered-ihs-in-the-near-future

Sounds like a simple "Hey, I have a thought, let's make it a rumor and news" item to me (and knowing that website it likely is just that)

*Could, might, may in 'news' items always make me laugh

 

[Carfax83]

Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?

Considering how fast he's running the RAM, 67ns is terrible. I get 53ns on my 6900K with DDR4 3200 CL14. Likely it's just a bug though, so we'll see if the numbers improve with a software or BIOS update.

 

[scannall]

[RUMOR] Intel will release Skylake-X SKUs with soldered IHS in the near future
According to our sources, Intel could release in the near future (4Q17 or 1Q18) the Skylake-X SKUs with soldered IHS.

source - http://www.bitsandchips.it/52-engli...e-x-skus-with-soldered-ihs-in-the-near-future

Like most rumors, read it for amusement value with a very large grain of salt.

 

[Hail The Brain Slug]

Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?

But cache results are disappointing.

5Ghz Kaby has:

same L1 ( 0.8ns or 4 cyckes)
way much better L2 ( 2.4ns vs 4.6ns here, but could be fluke result as it is very sensitive to timing, 4.6ns is 20+ cycles???)
and L3 is sub 10ns for 4.X ghz uncore.

So yeah, I can see why some of the tests are suffering.

Well, I would figure the actual memory latency for 3733 at CL17 should be lower than 3000 at CL14, yet the latency is ~15ns higher.

 

[Carfax83]

Well, I would figure the actual memory latency for 3733 at CL17 should be lower than 3000 at CL14, yet the latency is ~15ns higher.

Yeah but your uncore frequency is over 1.3ghz faster. Uncore frequency affects synthetic memory performance in a big way.

 

[JoeRambo]

Well, I would figure the actual memory latency for 3733 at CL17 should be lower than 3000 at CL14, yet the latency is ~15ns higher.

On ~same uncore and DDR4 3000 CL13, 7700K is getting ~42ns, so quad channel penalty is ~10ns.

So when 3Ghz uncore is accounted for, that is okayish result, not disaster that it would look like.

Now IF Skylake-X is actually unable to rise Uncore clocks, then we have a perfect storm of forum policy violating material: memory latency is high and at same time L3 is small and slow. That would not be nice.

 

[jpiniero]

BTW, the die size has also grown quite a bit.

Broadwell-E 10C die is like 240; Skylake-X 10C die is around 325.

By my totally reliable estimations by looking at the die pict, the core size (inc L3) is about 17 mm2. Kaby Lake is by the same estimation 12.2 mm2.

 

[csbin]

BTW, the die size has also grown quite a bit.

Broadwell-E 10C die is like 240; Skylake-X 10C die is around 325.

By my totally reliable estimations by looking at the die pict, the core size (inc L3) is about 17 mm2. Kaby Lake is by the same estimation 12.2 mm2.

Broadwell-E LLC 10C
Skylake-X LLC 12C

 

[jpiniero]

Broadwell-E LLC 10C
Skylake-X LLC 12C

It's 10. I can't come up with a chop that would make sense and end up with 12.

The MCC looks like this:

CCCC
MCCM
CCCC
CCCC
CCCC

The HCC looks like this:

CCCCC
MCCCM
CCCCC
CCCCC
CCCCC

Presumably the LCC is just this:

CCCC
MCCM
CCCC

 

[Timmah!]

It's 10. I can't come up with a chop that would make sense and end up with 12.

The MCC looks like this:

CCCC
MCCM
CCCC
CCCC
CCCC

The HCC looks like this:

CCCCC
MCCCM
CCCCC
CCCCC
CCCCC

Presumably the LCC is just this:

CCCC
MCCM
CCCC

Maybe LCC does not have 2 memory controllers, at which point your theory goes down the drain, cause unlike the MCC and XCC the LCC die does look completely different.

 

[IntelUser2000]

Could it not be the guy at the video put the Uncore only at 3GHz to get high CPU overclocks?

If the Uncore is responsible for L3 cache performance then the latency is really not different from Kabylake per clock.

The uncore is at 2xxxMHz. It's really low.

 

[jpiniero]

Maybe LCC does not have 2 memory controllers, at which point your theory goes down the drain, cause unlike the MCC and XCC the LCC die does look completely different.

Each of the memory blocks has 3 channels, or at least would make sense to me. So it needs two blocks.

 

[wildhorse2k]

Presumably the LCC is just this:

CCCC
MCCM
CCCC

Which makes the poor memory latency very surprising given the improved non-inclusive cache, mesh topology and max distance to memory controller being 4 instead of 5 on ring bus. We should be seeing lower latencies, not higher.

 

[TheF34RChannel]

Which makes the poor memory latency very surprising given the improved non-inclusive cache, mesh topology and max distance to memory controller being 4 instead of 5 on ring bus. We should be seeing lower latencies, not higher.

Exactly! Something is amiss with the reviews we saw (both sites are owned by the same company, FYI), I say. The better reviews cannot come soon enough!

 

[Sweepr]

Hope no one is done X299 testing & taking weekend off! Newest BIOes from last 48hrs provide significant perf uplift. Time to retest.....

https://twitter.com/hardwarecanucks/status/876162292139909120

Uplift are across the range of processors.

https://twitter.com/hardwarecanucks/status/876168415966355459

 

[jpiniero]

https://twitter.com/hardwarecanucks/status/876162292139909120

Do you really need to post this here considering it was mentioned in the other thread?