wildhorse2k
Member
- May 12, 2017
- 180
- 83
- 71
Needless to say Intel will have to fix the memory latency, write memory performance and poor VRMark performance or many people could be put off from going into X299. Not to say competition product will be better.
Intel seems to be doing some real smart things with LLC. While data is not inclusive, tags are. So that removes some of my fears about server CPUs suffering hard in thread communication.
Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?
But cache results are disappointing.
5Ghz Kaby has:
same L1 ( 0.8ns or 4 cyckes)
way much better L2 ( 2.4ns vs 4.6ns here, but could be fluke result as it is very sensitive to timing, 4.6ns is 20+ cycles???)
and L3 is sub 10ns for 4.X ghz uncore.
So yeah, I can see why some of the tests are suffering.
Core i9-7900X final rock stable 4,7 GHz, 3 GHz unCore, 3733 MHz Quad mem-channel
Final, 24/7 Core i7-7900X settings ... 4,7 GHz at 1,25V. 3 Ghz unCore at "Auto", memclock 3733 MHz quad channel. Not bad i think
AIDA has no full support for X299, BCLK, CPU clock, MEM clock are not correct. Look at CPUz screen, there is all OK
[RUMOR] Intel will release Skylake-X SKUs with soldered IHS in the near future
According to our sources, Intel could* release in the near future (4Q17 or 1Q18) the Skylake-X SKUs with soldered IHS.
source - http://www.bitsandchips.it/52-engli...e-x-skus-with-soldered-ihs-in-the-near-future
Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?
Like most rumors, read it for amusement value with a very large grain of salt.[RUMOR] Intel will release Skylake-X SKUs with soldered IHS in the near future
According to our sources, Intel could release in the near future (4Q17 or 1Q18) the Skylake-X SKUs with soldered IHS.
source - http://www.bitsandchips.it/52-engli...e-x-skus-with-soldered-ihs-in-the-near-future
Isn't 67ns vs ~40ns (for ~DDR4 3600 dual) quite good result for quad channel system?
But cache results are disappointing.
5Ghz Kaby has:
same L1 ( 0.8ns or 4 cyckes)
way much better L2 ( 2.4ns vs 4.6ns here, but could be fluke result as it is very sensitive to timing, 4.6ns is 20+ cycles???)
and L3 is sub 10ns for 4.X ghz uncore.
So yeah, I can see why some of the tests are suffering.
Well, I would figure the actual memory latency for 3733 at CL17 should be lower than 3000 at CL14, yet the latency is ~15ns higher.
Well, I would figure the actual memory latency for 3733 at CL17 should be lower than 3000 at CL14, yet the latency is ~15ns higher.
BTW, the die size has also grown quite a bit.
Broadwell-E 10C die is like 240; Skylake-X 10C die is around 325.
By my totally reliable estimations by looking at the die pict, the core size (inc L3) is about 17 mm2. Kaby Lake is by the same estimation 12.2 mm2.
Broadwell-E LLC 10C
Skylake-X LLC 12C
It's 10. I can't come up with a chop that would make sense and end up with 12.
The MCC looks like this:
CCCC
MCCM
CCCC
CCCC
CCCC
The HCC looks like this:
CCCCC
MCCCM
CCCCC
CCCCC
CCCCC
Presumably the LCC is just this:
CCCC
MCCM
CCCC
Maybe LCC does not have 2 memory controllers, at which point your theory goes down the drain, cause unlike the MCC and XCC the LCC die does look completely different.
Presumably the LCC is just this:
CCCC
MCCM
CCCC
Which makes the poor memory latency very surprising given the improved non-inclusive cache, mesh topology and max distance to memory controller being 4 instead of 5 on ring bus. We should be seeing lower latencies, not higher.
Hardware Canucks said:Hope no one is done X299 testing & taking weekend off! Newest BIOes from last 48hrs provide significant perf uplift. Time to retest.....
Hardware Canucks said:Uplift are across the range of processors.