That toothpaste is crap. I won't buy coffee lake for sure if it has that junk TIM under the hood.
Yeah, well, that's what it's going to have...That toothpaste is crap. I won't buy coffee lake for sure if it has that junk TIM under the hood.
Those are allowed what, 65-70°C before they completely shut down?soldered CPU seems to be working fine on AMD's FX line space heaters, no pun intended.
Those are allowed what, 65-70°C before they completely shut down?
So less heat less problems?
What no igpu to add to the heat/space problem?
Oh,they also have like twice the area?
Look at previous page convienently posted by tamz_msc jumps from below 30 to above 70...and your point is? micro cracks will occur due to stress caused by rapid spike/fluctuations temps. the magnitude of the spike and the freq are the main concerns and not the maximum attainable temp, there are solder pads that work just fine at 200C. true, the lower limit will mean lower magnitude of the spike, but i am yet to see any CPU jump from 30 C to 70C in less than one-second. so it means nothing.
Do I seriously have to search for a die size pic of APU now?last i checked, AMD also has CPU+iGPU configs. which ironically uses solder pads. having said that a iGPU free CPU on its own can draw more power than CPU+iGPU.
You are forced to cool them harder,which makes the cooler blow more heat into your room,yes.unless after all these years you want to say FX line runs cooler than intel. is that what you mean?
Read the link I posted, the TIM forms cracks not the silicon,exactly because most of the time only some areas of the chip get hot at any o time the TIM at that spot gets hotter then the rest of the TIM repeat for hundreds of cycles and the TIM weakens at those spots with cracks being the result.what does die area have to do with anything, unless you want to say the rise time of the spike are long enough for the heat to be spread out throughout the entire CPU, which is not the case, as you will see that cpu core temps can vary based on CPU usage even after prolonged single threaded load
Void and micro crack occurrence is mainly affected by the solder area – thus the DIE size. Small DIE size (below 130 mm²) e. g. Skylake will facilitate the void occurence significantly. However, CPUs with a medium to large DIE size (above 270 mm²) e. g. Haswell-E show no significant increase of micro cracking during thermal cycling (Figure 12).
I can see from XTU that my 4790K throttles right at 99-100C core temp on the nose.What's interesting is that in the official specifications, Intel lists the Tcase when it comes to the 3770K, 4770K, 4790K and 6700K. It's only in the case of the 7700K that Tjunction is specified instead of Tcase.
1. so? its showing the 7700 which has problems.1. Look at previous page convienently posted by tamz_msc jumps from below 30 to above 70...
2. Do I seriously have to search for a die size pic of APU now?
246 on line with sandy the last die that had solder for intel according to previous posts.
3. You are forced to cool them harder,which makes the cooler blow more heat into your room,yes.
4. Read the link I posted, the TIM forms cracks not the silicon,exactly because most of the time only some areas of the chip get hot at any o time the TIM at that spot gets hotter then the rest of the TIM repeat for hundreds of cycles and the TIM weakens at those spots with cracks being the result.
Yes the test scenario for failure prediction is unrealistic that's how every stress test for any material or product is being done.4. So? read the link yourself please: "thermal cycle is performed by going from -55 °C to 125 °C while each temperature is hold [held] for 15 minutes" very realistic. don't quote academic studies, find me a "small" CPU that failed. Let me sort you out a little: AMD Athlon 64 is 103.1 mm² and a Max temp of 78 C. so now you know what CPU you have to find that developed a crack!
Over a long time scale if there were short duration spikes they might not be pick up by the OCCT graph. This isn't the case however.KL may simply have a better sensor that is more accurate and responds quicker.
People are reporting these spikes with CPU:OCCT. Does it use AVX2? I'm pretty sure if they used LINPACK which does support AVX2 their CPUs would shut down in minutes.You'd think people would know by now that AVX2 causes Core to become a space heater, esp at 4+ Ghz.
Intel CPUs down clock themselves when it is running AVX codes irrespective of temps. So the effect should be not be anything that is different from normal usage.You'd think people would know by now that AVX2 causes Core to become a space heater, esp at 4+ Ghz.
one AVX instruction on one core forced all cores on the same socket to slow down their clockspeed by around 2 to 4 speed bins (-200,-400 MHz) for at least 1 ms,
Intel CPUs down clock themselves when it is running AVX codes irrespective of temps. So the effect should be not be anything that is different from normal usage.
That guy poking the chip is der8auer. He killed 2 of 3 chips when he tried the initial delid with Ryzen.
I'd have to think that doesn't apply when OCing unless you use the AVX offset.
Separate multipliers for AVX workloads were introduced in the E5 2600v3. AVX offset is a feature in the BIOS introduced with Z270. http://www.intel.com/content/dam/ww...on-e5-v3-advanced-vector-extensions-paper.pdfI'd have to think that doesn't apply when OCing unless you use the AVX offset.
I would think a LINPACK shutdown problem for KL would have been big news long ago...as would a loss of throttle ability...People are reporting these spikes with CPU:OCCT. Does it use AVX2? I'm pretty sure if they used LINPACK which does support AVX2 their CPUs would shut down in minutes.