Intel to Detail 14nm Process on August 11

[FatherMurphy]

Cool, thanks. I think SIGGRAPH is also starting next week, and Nvidia is presenting there as well. http://www.nvidia.com/object/siggraph2014.html

Fun times ahead!

 

[videogames101]

that would be your brain, sir

Nope, but you'd think most IC companies would already have data, if Intel actually plans to open up their fabs as they say.

 

[ninaholic37]

Nope

I think he's talking about how the human brain is more low power and faster than any current chip (or he's saying that you're dense, I'm not quite sure :hmm: ).

edit: Wait! I noticed that he changed faster to "fatter", so I guess he was saying that you have a giant ego (fatter) but not much thought process (low power).

 

[videogames101]

I think he's talking about how the human brain is more low power and faster than any current chip (or he's saying that you're dense, I'm not quite sure :hmm: ).

edit: Wait! I noticed that he changed faster to "fatter", so I guess he was saying that you have a giant ego (fatter) but not much thought process (low power).

Such subtlety D:

 

[Homeles]

Do we have confirmed technical specs of the 20nm, 16nm, or 14nm TMSC or Samsung processes?

I can't link to sources atm, but I'm fairly certain we know the specs for all three. M1 pitch is 64nm on 20/16/16+/14.

Intel's rumored to be targeting a smaller pitch. I saw someone in another thread source an insider that said it'd be 60nm, and the R&D firm Imec states that 14nm processes will have M1 pitches as low as 58nm.

Therefore, preliminary information indicates that Intel will have a small density lead. I haven't seen transistor performance figures for any next gen process, but it stands to reason that Intel will lead here considerably, as they have done for the past decade(s).

 

[Fjodor2001]

Looking at all the stuff Intel will present on Monday, what's new info left for IDF?

EDIT: Sorry, I just checked the links in that post more closely, and they are for IDF. But then my original question is still left to be answered I guess, i.e. where can we find details on what info Intel will cover in the presentation on Monday?

 

[SAAA]

Looking at all the stuff Intel will present on Monday, what's new info left for IDF?

EDIT: Sorry, I just checked the links in that post more closely, and they are for IDF. But then my original question is still left to be answered I guess, i.e. where can we find details on what info Intel will cover in the presentation on Monday?

I guess they will talk about 14nm tech before, then detail Broadwell architecture at IDF.
I still hope there is some talk about Skylake considered how many rumors of a '15 release and how many samples are being built (look at any import/export site and notice the traffic!).

 

[Khato]

I can't link to sources atm, but I'm fairly certain we know the specs for all three. M1 pitch is 64nm on 20/16/16+/14.

Intel's rumored to be targeting a smaller pitch. I saw someone in another thread source an insider that said it'd be 60nm, and the R&D firm Imec states that 14nm processes will have M1 pitches as low as 58nm.

Good thing that there's far more to a process than the M1 pitch eh? For example, design rules are likely different, which can have a marked effect upon how often that minimum M1 pitch can actually be used. Sure it's fun to throw around various buzzwords to 'prove' which process is superior, but it's not terribly productive.

 

[mavere]

Do we have confirmed technical specs of the 20nm, 16nm, or 14nm TMSC or Samsung processes?

Supposed numbers from BNP Paribas:

They also think that Intel's 14nm will have 63nm M1 pitch. As for the contacted gate pitch, Chipworks believe we'll see something around 60nm. Those numbers would also match well with the scaling trend for Intel's nodes:

 

[Homeles]

Good thing that there's far more to a process than the M1 pitch eh? For example, design rules are likely different, which can have a marked effect upon how often that minimum M1 pitch can actually be used. Sure it's fun to throw around various buzzwords to 'prove' which process is superior, but it's not terribly productive.

It's an important metric. Please stop trying to marginalize that.

Intel's very likely to have the densest node out of the biggest three players. A smaller metal pitch is a critical piece in ensuring that. The expectation going into next week, by those of us that have done the proper research (yet don't have insider information), should be that Intel will have a slight lead here. There's room for skepticism of course, but that's the way things look from an objective eye.

What's gotten into you? You're usually better informed than this.

 

[Khato]

It's an important metric. Please stop trying to marginalize that.

Important yes, but if one were to read these forums without full technical understanding they'd think that it's the metric for determining the density of a process. If that actually was the case then why precisely did Intel use a 90nm M1 for 22nm while M2 and M3 are 80nm? If they're capable of the finer geometry then why didn't they use it for this most important metric? Fact is that there's a lot more going on when it comes to density than just the M1 pitch - Intel's M1 being 1D for example.

Intel's very likely to have the densest node out of the biggest three players. A smaller metal pitch is a critical piece in ensuring that. The expectation going into next week, by those of us that have done the proper research (yet don't have insider information), should be that Intel will have a slight lead here. There's room for skepticism of course, but that's the way things look from an objective eye.

What's gotten into you? You're usually better informed than this.

Eh, such is the result of being far more skeptical of TSMC's claims than usual. Why? Because they're sounding a lot more like AMD/GF with respect to loudly proclaiming how they're going to catch up to Intel with this extremely aggressive roadmap that likely won't bear much resemblance to reality. Both their refute of Intel's chart regarding 14nm class density (sorry, but TSMC has far less information regarding Intel's 14nm process than Intel has regarding TSMC's '16nm') and their announcement of FinFET+ were straight out of the AMD/GF playbook - promise now, make excuses later. Meanwhile Samsung is comparatively hard to read in that respect, I'd guess in large part because it's merely one branch of a large conglomerate and hence not in a life or death fight with Intel. However it's clear that they're interested in turning it into more of a business than it currently is, so there's still quite a bit of PR fluff to be found there.

And, of course, I still don't really expect either Samsung or TSMC to be able to meet their current schedules for high volume manufacturing. But it's still a bit early for there to be hard information supporting that suspicion. If they still haven't started orders for equipment for their finFET processes at the end of the current quarter though...

 

[witeken]

As for the contacted gate pitch, Chipworks believe we'll see something around 60nm. Those numbers would also match well with the scaling trend for Intel's nodes:

Have you also read why they think that? It's because "The scaling of Intel’s CMOS technology has continued to follow Moore’s Law for the past ten years, with the contacted gate pitch scaling as approximately 4X the technology node. Each node corresponds to a shrink by a factor of 0.7, which corresponds to a doubling of the density of transistors per unit area."

So this estimate is just based on extrapolation, which is logical because this article was written in 2012.

I do expect a smaller gate:

 

[witeken]

It's an important metric. Please stop trying to marginalize that.

Intel's very likely to have the densest node out of the biggest three players. A smaller metal pitch is a critical piece in ensuring that. The expectation going into next week, by those of us that have done the proper research (yet don't have insider information), should be that Intel will have a slight lead here. There's room for skepticism of course, but that's the way things look from an objective eye.

What's gotten into you? You're usually better informed than this.

That are some incredibly bold claims. You should know this Homeles, if you make such claims, you need sources to back up what you say.

If you don't, why should I believe you? So I remain supportive of this slide:

 

[carop]

If that actually was the case then why precisely did Intel use a 90nm M1 for 22nm while M2 and M3 are 80nm? If they're capable of the finer geometry then why didn't they use it for this most important metric? Fact is that there's a lot more going on when it comes to density than just the M1 pitch - Intel's M1 being 1D for example.

The resolution capability of a system - the minimum feature that can be printed - is described by the Rayleigh equation:

Resolution = k1 Lamda / NA

A larger k1 factor means that the lithographic process control is easier and the yield is higher. Usually, a k1 factor above 0.30 is needed for production and k1 cannot typically go below 0.25. A lithographic process in which 0.25 < k1 < 0.30 is difficult and requires very aggressive resolution enhancement techniques.

Using a 193i immersion tool with NA = 1.35, a 80nm pitch requires a k1 factor that is less than 0.30.

Regardless of transistor choice, whether bulk planar, FD-SOI, or FinFET, each transistors need three contacts and routing metals. This is why the metal 1 pitch is important since the transistors are dwarfed by the metal 1 layer. With FinFET devices, the fin pitch becomes the dominant factor for SRAM layout:

In the ITRS System Drivers Chapter and Overall Roadmap Technology Characteristics, A-factors enable the modeling of unit cell
areas of SRAM and standard-cell logic circuit fabrics, in terms of the M1 half-pitch, F. SRAM layout density is mainly determined by Mx pitches and poly pitch in a bulk technology. With FinFET devices, the fin pitch (Pf in) becomes the dominant factor for SRAM layout. On the other hand, the density of standard cells is mainly decided by the cell height (in M2 tracks) and the poly pitch. Since the 2009 ITRS, the A-factor for a 6T SRAM bitcell has been 60F2, and the A-factor for a 2-input NAND gate has been 175F2 [10]. These values are based on various ratios between, e.g., poly, M1, and M2 layer pitches (design rules) as summarized in the left half of Table 1, as well as on the canonical layouts shown in Figures 4(b) and 5(b) [10].

http://vlsicad.ucsd.edu/Publications/Conferences/302/c302.pdf

The Intel 14nm node appears to be a node shrink of their 22nm node. However, I think the most important question is weather the Intel SRAM design is continuing to sit on the usual area scaling trend.

1D gridded layouts provide better overlay between M1 and M2 layers, and SADP has better OPC than LELE. Nevertheless, there are some results showing that the operating voltage do not scale in the same proportion as the logic devices on the same die. As such, the fundamental trade off is between cell stability and area.

An SRAM cell size smaller than 0.05µm2 will be impressive. But, I would not be surprised if their memory design is not sitting on the area scaling trend.

 

[jpiniero]

You know I just realized that Intel slide about the scaling is just taking advantage of TSMC's marketing hijinx with the nodes. I imagine we will see TSMC's "10 nm" before Intel's real one though.

 

[Fjodor2001]

Just so we're clear, nobody actually knows the details of what info Intel intends to present at the event on Monday, right? All we know is the title of it, which is "Advancing Moore's Law in 2014"... ?

 

[ninaholic37]

Just so we're clear, nobody actually knows the details of what info Intel intends to present at the event on Monday, right? All we know is the title of it, which is "Advancing Moore's Law in 2014"... ?

The title sounds like they will be updating the definition of Moore's Law, doesn't it? Maybe "advancing" is a nice way of saying "changing". D:

 

[jdubs03]

You know I just realized that Intel slide about the scaling is just taking advantage of TSMC's marketing hijinx with the nodes. I imagine we will see TSMC's "10 nm" before Intel's real one though.

Doubt it. 16FF/+ will be a year out from Intel's 14nm. They'd have to close down another year to release at the same time. I don't expect that to happen, in fact Intel's lead could increase, as TSMC may have an issue with lowering the density from its 16FF+ (20nm BEOL) to its 10nm process (14nm BEOL). Keep in mind Samsung is ahead of TSMC now, so they might have a better shot at retaining the status quo in terms of process. If Samsung is using similar parameters that TSMC is, they could run into problems too. Intel already went through these issues, and from what I have gathered they can apply that experience to 10nm, so there shouldn't be a delay like 14nm.

 

[Xpage]

but 10nm will be the III-V materials, so many new things will be introduced. The experience may help but all new technical issues will be present

 

[jpiniero]

Doubt it. 16FF/+ will be a year out from Intel's 14nm. They'd have to close down another year to release at the same time.

I'm not expecting Intel to release 10 nm products until 2017 at the earliest, and likely well into it. That's where I see the delay. I see TSMC's fake 10 nm sometime in 2016... but oh btw, I don't see anyone other than Intel releasing real 10 nm products until (if?) EUV shows up.

 

[jdubs03]

but 10nm will be the III-V materials, so many new things will be introduced. The experience may help but all new technical issues will be present

Hopefully you're right with the III-V, I think you may be, hopefully IDF will give us the answer to that.

 

[Arachnotronic]

Hopefully you're right with the III-V, I think you may be, hopefully IDF will give us the answer to that.

I don't think so. Intel will not signal what it's doing with 10-nanometer until 10-nanometer products are in production.

Why tell your competitors what to do next earlier than you need to?

 

[jdubs03]

I don't think so. Intel will not signal what it's doing with 10-nanometer until 10-nanometer products are in production.

Why tell your competitors what to do next earlier than you need to?

Well they did do that with announcing Tri-gate back in 2011, so it may not be out of the question. But, on the other hand, considering that Intel has been holding their cards closer to the vest, they could be playing the waiting game.

My guess is, since they're allegedly showing off a 10nm wafer at IDF, they may hint at what was improved upon for them to have a successful wafer in front of the audience, and that could be III-V. They usually beat everyone else to new improvements, the foundries will have III-V at 7nm (10nm BEOL?), so the only way to stay ahead in the process game is to adopt III-V for 10nm vis a vis Tri-gate at 22nm versus 16FF TSMC/14nm Samsung.

*Maybe you were just disagreeing with the announcement?, or are you skeptical of 10nm being III-V?

 

[witeken]

I'm not expecting Intel to release 10 nm products until 2017 at the earliest, and likely well into it. That's where I see the delay. I see TSMC's fake 10 nm sometime in 2016... but oh btw, I don't see anyone other than Intel releasing real 10 nm products until (if?) EUV shows up.

Let me correct the things you said in this post.

1) 10nm is projected by Intel for a 2016 release.
2) Intel stated HVM in 2015.
3) According to Brian Krzanich, Intel hasn't changed its 10nm schedule, even though 14nm is delayed by half a year.
4) Intel doesn't need EUV for their 10nm node.
5) We know from multiple sources that 10nm will introduce Germanium or III-V, which will vastly improve transistor characteristics so it will be superior to FinFET.
6) TSMC's 20FF is expected to ship in mass products in 2016. 2015 will be 20nm.
7) TSMC says their 10nm node (with 3rd generation FinFET) is scheduled to launch 2 years after their 16nm node, so early 2018 is the most optimistic release for 10nm (=14FF) products, but I'd rather put my money on late 2018.

 

[USER8000]

So one set of PR vs another set of PR - awesome!:thumbsup:

I predict the following from all parties:
1.)Our tech is better than the competition
2.)Our tech is cheaper than the competition
3.)Our tech is more reliable than the competition
4.)Our tech will be quicker to market than the competition

If in reality the tech does not actually pan out as well as planned it will be "our future tech" will be:
1.)better than the competition
2.)cheaper than the competition
3.)more reliable than the competition
4.)will be quicker to market than the competition

Rinse and repeat.

Its hardly like company PR won't big up their own products and slam the competition's competing products and services.