Intel to Detail 14nm Process on August 11

[witeken]

Moorefield was always planned to launch in Q3.

 

[Hans de Vries]

The timing was mere coincidence, trust me.

The reason Intel has been tight-lipped about 14nm is because the competition (foundry-wise) isn't/can't do a BEOL shrink at their respective 14nm'ish nodes.

I don't know what your expectations are but Intel's 14nm process needs
an interconnect pitch of ~56nm for 1D interconnect to match the logic
density of the 64nm pitch for 2D interconnect as used in the 20nm processes
of the foundries.

This 56nm was Intel's goal for the 15/14nm node. See the slide below.
(56nm = 112.5 * 0.71 * 0.71)

For the previous generation (22nm) Intel's goal was 80nm, which they
missed a bit for the Metal 1 pitch which is 90nm instead.

I don't think Intel's interconnect goals have become more aggressive,
why would they take the risk? The scaling factor 2.2 as often mentioned
may also include extra scaling from going from manual layout to denser
automated layout generation, for instance.

Hopefully we will know more today, but I don't know since it will be a
presentation for investors.....

 

[witeken]

I don't know what your expectations are but Intel's 14nm process needs
an interconnect pitch of ~56nm for 1D interconnect to match the logic
density of the 64nm pitch for 2D interconnect as used in the 20nm processes
of the foundries.

This 56nm was Intel's goal for the 15/14nm node. See the slide below.
(56nm = 112.5 * 0.71 * 0.71)

For the previous generation (22nm) Intel's goal was 80nm, which they
missed a bit for the Metal 1 pitch which is 90nm instead.

I don't think Intel's interconnect goals have become more aggressive,
why would they take the risk? The scaling factor 2.2 as often mentioned
may also include extra scaling from going from manual layout to denser
automated layout generation, for instance.

It has become more aggressive, according to Intel. Your slide is from 2009, lots of things have changed since then.

Hopefully we will know more today, but I don't know since it will be a
presentation for investors.....

Which Intel presentation for investors is today?

 

[Fjodor2001]

Which Intel presentation for investors is today?

Maybe the presentation in the OP? I.e. this presentation, which this whole thread is supposed to be about. You can follow it via webcast (see info at the link). Or are there more presentations by Intel today?

 

[witeken]

Maybe the presentation in the OP? I.e. this presentation, which this whole thread is supposed to be about. You can follow it via webcast (see info at the link). Or are there more presentations by Intel today?

Interesting, I didn't look at the date for this Advancing Moore’s Law in 2014! presentation. I thought it was one of the presentations at IDF.

“This briefing will include technical disclosures for the upcoming Broadwell SoC, as well as provide updates on Intel’s new 14nm process node.” This webcast is in webinar format.

We already know everything about Broadwell-Y, but the update on the 14nm process node should be interesting.

 

[Hans de Vries]

It has become more aggressive, according to Intel. Your slide is from 2009, lots of things have changed since then.

Which Intel presentation for investors is today?

You can't draw that conclusion from this marketing slide.

As I said, a higher transistor density does not always need to come from
process improvements. Especially Intel uses a lot of traditional manual
layout in its designs. Manual layout helps for some purposes but in general
the transistor density gets lower as a result, often significantly lower.

If Intel is planning to use improved automated layout tools for coming
process generations for larger portions of the chip then the overall
transistor density will also improve. This is actually what we see happening
if we look at Intel chips. The difference between manual and automated
layout is clearly visible.

So, I wouldn't be surprised if this explains the factor 2.2.

 

[ame132]

“This briefing will include technical disclosures for the upcoming Broadwell SoC, as well as provide updates on Intel’s new 14nm process node.” This webcast is in webinar format.

from webcast

 

[witeken]

Now live.

http://intelstudios.edgesuite.net/140811_intel/event.html

 

[mikk]

http://pics.computerbase.de/5/9/1/8/8/3.png
http://www.anandtech.com/show/8355/intel-broadwell-architecture-preview

 

[Homeles]

52nm? Goodness.

Also, yay die shot.

5% IPC.

 

[Phynaz]

http://techreport.com/review/26896/i...essor-revealed

 

[Arachnotronic]

52nm minimum metal pitch, 70nm gate pitch, and 42nm fin pitch. 0.0588um^2 SRAM cell. Very nice.

 

[witeken]

Key announcements / Summary:

1st presentation, Broadwell-Y innovations:
14nm transistor, lower TDP, < 9mm fanless designs, lower idle power (60%), 2nd gen FIVR & 3DL, Broadwell Core, better graphics and chipset

Platform innovations:
14nm: "2X lower TDP with better performance"; 25% smaller board area and 50% die area; enhanced Turbo Boost

So all sorts of techniques to reduce power.

Mark Bohr's presentation about 14nm:
14nm qualified and HVM

Fin Pitch: 60->42 (0.7x)
Gate pitch: 90->70 (0.8x)
Interconnect/minimum pitch: 80->52 (0.65x) (2.3x lower)

Higher thin height 34->42
Fewer gates needed for even greater area reduction.

2x SRAM cell reduction: 0.0588um^2 SRAM vs 0.110µm
>2X improvement in perf/watt (instead of ~1.6x)

Reiterating scaling vs competition (like infamous slide from 2013). 10nm based on VLSI 2014 information. Intel nailed it, this graph is way less ambiguous than that from the Investor Meeting . BTW, much re-use of slides, updated with 14nm.

Yields: on target for multiple 14nm ramps in H1'15.


3rd presentation, Broadwell microarchitecture disclosures:

Slide about thickness and needed TDP: 10" and 7mm equals 3W TDP => 3-5W TDPs necessary

Capacitance: 0.65x lower -> 25% lower power
Voltage: 10% lower -> 25% lower power
ULV performance: 10-15% higher perf
Leakage: 2X lower instead of 0.8x scaling -> 10% lower power
Die scaling: 0.63x in real world (we already calculated that with the Broadwell-Y die shown at IDF2013)
50% smaller XY, 30% smaller Z
New PCH (details at IDF)

2nd gen FIVR with more capacitors: better efficiency at low voltages

Enhanced power management:
Turbo boost: PL1: long term system limit; PL2: burst limit (decided by OEM); PL3: protection of battery
Platform power sharing

SoC power reduction:
designed to reduce minimum voltage, optimized fro Cdyn reduction, major re-arch of DDR/IO/PLL/graphics, microarch optimizations for IA, chipset and graphics.

Broadwell arch:
CPU: 5% IPC, designed at 2:1 performanceower ratio
GPU: Gen8, UHD, media improvements

 

[witeken]

14nm clearly doesn't disappoint, doing even better than predicted (2.36x instead of 2.2x). Also interesting platform innovations with 2nd gen FIVR and 3DL (don't know what that is).

BTW, anyone knows where to find the slides?

 

[ShintaiDK]

The transistor/cost vs the competition is simply overwhelming. Cost drops as expected fro Intel. Samsung/TSMC price per transistor increases.

It also shows Intels massive lead technology wise. Its getting close to 4 year lead now.

 

[Hans de Vries]

Okay, They went from 56nm down to 52nm

 

[raghu78]

The transistor/cost vs the competition is simply overwhelming. Cost drops as expected fro Intel. Samsung/TSMC price per transistor increases.

It also shows Intels massive lead technology wise. Its getting close to 4 year lead now.

massive lead. Don't talk rubbish. Here we are talking about the so called Intel "true 14nm process" against Samsung 14nm .

Intel 14nm SRAM cell - 0.0588 um^2
Samsung 14nm SRAM cell - 0.064 um^2
TSMC 16FF - 0.070 um^2
TSMC 16FF+ - roughly 0.060 um^2 (15% lesser size)

Intel 14nm contacted gate pitch - 70nm
Samsung 14nm contacted gate pitch - 77nm
TSMC 16FF - 90 nm
TSMC 16FF+ - roughly 78-79 nm (15% size reduction)

This proves all the talk about Intel's density advantage was just hype. The intel loyalists were boasting a 30% density advantage over the foundries 14/16 nm. Reality <= 10% . So since Intel loyalists called the foundries 14/16nm FINFET as 20nm FINFET what is Intel's 14nm now called ? 18nm FINFET.

 

[Arachnotronic]

massive lead. Don't talk rubbish. Here we are talking about the so called Intel "true 14nm process" against Samsung 14nm .

Intel 14nm SRAM cell - 0.0588 um^2
Samsung 14nm SRAM cell - 0.064 um^2
TSMC 16FF - 0.070 um^2
TSMC 16FF+ - roughly 0.060 um^2 (15% lesser size)

Intel contacted gate pitch - 70nm
Samsung contacted gate pitch - 77nm
TSMC 16FF - 90 nm
TSMC 16FF+ - roughly 78-79 nm (15% size reduction)

This proves all the talk about Intel's density advantage was just hype. The intel loyalists were boasting a 30% density advantage over the foundries 14/16 nm. Reality <= 10% . So since Intel loyalists called the foundries 14/16nm FINFET as 20nm FINFET what is Intel's 14nm now called ? 18nm FINFET.

Intel's Mark Bohr claimed that logic density could be approximated by minimum metal pitch * contacted gate pitch, and on that metric, Intel is quite a bit ahead.

Oh, and unlike TSMC -- which expects to begin volume production of 16 FinFET in late 2015 -- Intel is in production now.

Finally, source for the TSMC 16 FinFET+ density numbers, please? I'm fairly confident that 16 FinFET+ improves transistor performance, not gate pitch or metal pitch.

EDIT: SRAM density is dominated by gate/fin pitch, I believe.

 

[VirtualLarry]

Sounds really great. Can't wait to see some nice integrated mini-ITX mobos based on Broadwell (whatever flavor is appropriate for that form factor). Should be very power-efficient, and fast too.

 

[Homeles]

The FinFETs on Intel's 14nm process are squared off, which is supposedly better for transistor performance. Interesting. They're also cutting down on the number of fins they're using, as they don't need as many to reach their desired amperage targets.

 

[Guest1]

massive lead. Don't talk rubbish. Here we are talking about the so called Intel "true 14nm process" against Samsung 14nm .

Intel 14nm SRAM cell - 0.0588 um^2
Samsung 14nm SRAM cell - 0.064 um^2
TSMC 16FF - 0.070 um^2
TSMC 16FF+ - roughly 0.060 um^2 (15% lesser size)

Intel 14nm contacted gate pitch - 70nm
Samsung 14nm contacted gate pitch - 77nm
TSMC 16FF - 90 nm
TSMC 16FF+ - roughly 78-79 nm (15% size reduction)

This proves all the talk about Intel's density advantage was just hype. The intel loyalists were boasting a 30% density advantage over the foundries 14/16 nm. Reality <= 10% . So since Intel loyalists called the foundries 14/16nm FINFET as 20nm FINFET what is Intel's 14nm now called ? 18nm FINFET.

Why are you comparing a finished product with paper specs and thinking you proved your point? ROFL

 

[witeken]

massive lead. Don't talk rubbish. Here we are talking about the so called Intel "true 14nm process" against Samsung 14nm .

Intel 14nm SRAM cell - 0.0588 um^2
Samsung 14nm SRAM cell - 0.064 um^2
TSMC 16FF - 0.070 um^2
TSMC 16FF+ - roughly 0.060 um^2 (15% lesser size)

Intel 14nm contacted gate pitch - 70nm
Samsung 14nm contacted gate pitch - 77nm
TSMC 16FF - 90 nm
TSMC 16FF+ - roughly 78-79 nm (15% size reduction)

This proves all the talk about Intel's density advantage was just hype. The intel loyalists were boasting a 30% density advantage over the foundries 14/16 nm. Reality <= 10% . So since Intel loyalists called the foundries 14/16nm FINFET as 20nm FINFET what is Intel's 14nm now called ? 18nm FINFET.

Intel's slides were compared to TSMC, not Samsung. AFAIK, all Intel's mobile competitors will use TSMC's process, which had a lower density than Samsung's process. Samsung's process is about the same as FF+. Intel was traditionally behind in density at every node, and now Intel is ahead by a nice margin that will be reduced by FF+, whenever that launches; in ~H2'16, I'd geuss. Intel is boasting a 2X efficiency improvement, on top of the 2X improvement Intel already got with 22nm. So Intel really is a lot ahead in area, power and TTM, about 3-4 years I'd say.

 

[witeken]

For those who missed it, here's my summary of the presentation.

Also, here's Intel's press release with imagery and the presentation (pdf).

Broadwell-Y and the 14nm process really seems to live up to the hype created by F. Piednoel . The only thing that's disappointed is the lack of information disclosed about Gen8, not even a marketing comparison slide (like efficiency advantage over Gen7).

 

[raghu78]

Intel's Mark Bohr claimed that logic density could be approximated by minimum metal pitch * contacted gate pitch, and on that metric, Intel is quite a bit ahead.

Oh, and unlike TSMC -- which expects to begin volume production of 16 FinFET in late 2015 -- Intel is in production now.

Finally, source for the TSMC 16 FinFET+ density numbers, please? I'm fairly confident that 16 FinFET+ improves transistor performance, not gate pitch or metal pitch.

EDIT: SRAM density is dominated by gate/fin pitch, I believe.

Contacted gate pitch determines area scaling.

http://www.vlsiconference.com/vlsi2010/keyNote/NanoelectronicsChallenges_AntoniadisMIT.pdf

page 17

&#8226;"Contacted gate pitch&#8221; is the key scaling parameter between successive CMOS generations ~ 30% reduction per generation
&#8226; Circuit density scales with &#8220;contacted gate pitch&#8221;

https://www.pdf.com/upload/File/Publications/Enabling_Technology_Scaling.pdf


"Circuit designers want to find the most efficient way of mapping transistors in a circuit to the transistors in layout. One of the primary necessities is to connect metal 1 polygons to the terminals of the transistor (in active or poly layer) using a contact. As a result, gates (poly over active) in IC layouts most often have a contact between them to access either the source or the drain of the respective transistor. It is imperative that the contacted gate pitch (poly pitch with a contact in between) is the most frequently occurring pitch for the poly layer instead of the minimum poly pitch. In our approach to design circuits with a limited number of grating&#8211;like patterns, we have to limit the pitches used for layout design. Since the contacted gate pitch is the most frequently occurring design pitch, we constrain the poly pitch for the FEOL limited regular design fabric to be the contacted gate pitch. Under such a constraint the horizontal scaling of the FEOL limited fabric is limited by the front&#8211;end of line rules. Specifically, to achieve higher transistor density we need to solve the integration challenges involved with scaling the contacted gate pitch and do not really care for the printability of the minimum poly pitch."

 

[Arachnotronic]

Contacted gate pitch determines area scaling.

http://www.vlsiconference.com/vlsi2010/keyNote/NanoelectronicsChallenges_AntoniadisMIT.pdf

"&#8226;Contacted gate pitch&#8221; is the key scaling parameter between successive CMOS generations ~ 30% reduction per generation
&#8226; Circuit density scales with &#8220;contacted gate pitch&#8221;

https://www.pdf.com/upload/File/Publications/Enabling_Technology_Scaling.pdf


https://www.pdf.com/upload/File/Publications/Enabling_Technology_Scaling.pdf

"Circuit designers want to find the most efficient way of mapping transistors in a circuit to the transistors in layout. One of the primary necessities is to connect metal 1 polygons to the terminals of the transistor (in active or poly layer) using a contact. As a result, gates (poly over active) in IC layouts most often have a contact between them to
access either the source or the drain of the respective transistor. It is imperative that the contacted gate pitch (poly pitch with a contact in
between) is the most frequently occurring pitch for the poly layer instead of the minimum poly pitch. In our approach to design circuits with a limited number of grating&#8211;like patterns, we have to limit the pitches used for
layout design. Since the contacted gate pitch is the most frequently occurring design pitch, we constrain the poly pitch for the FEOL limited
regular design fabric to be the contacted gate pitch. Under such a constraint the horizontal scaling of the FEOL limited fabric is limited by the front&#8211;end of line rules. Specifically, to achieve higher transistor density we need to solve the integration challenges involved with scaling the contacted gate pitch and do not really care for the printability of the
minimum poly pitch."

If contacted gate pitch solely determined area scaling, then Intel's 22nm FinFET process would have compared quite a bit more favorably in logic density compared to the modern 28nm processes.

For example, CGP of Samsung 28nm was ~120nm (link: http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/), but at 22nm FinFET for Intel, CGP was 90nm.

Metal pitch is where Intel has traditionally lagged on a named-node basis, which is why TSMC's density at named-nodes has been far more competitive than Intel's.