Intel to Detail 14nm Process on August 11

[AtenRa]

Okay, They went from 56nm down to 52nm

Is 52nm for M1 or M2 ??? because at 22nm M1 is 90nm not 80nm.

 

[USER8000]

So one set of PR vs another set of PR - awesome!:thumbsup:

I predict the following from all parties:
1.)Our tech is better than the competition
2.)Our tech is cheaper than the competition
3.)Our tech is more reliable than the competition
4.)Our tech will be quicker to market than the competition

If in reality the tech does not actually pan out as well as planned it will be "our future tech" will be:
1.)better than the competition
2.)cheaper than the competition
3.)more reliable than the competition
4.)will be quicker to market than the competition

Rinse and repeat.

Its hardly like company PR won't big up their own products and slam the competition's competing products and services.

What else could it be?
No. That's not how these things work -- not even close.

They're publishing the technical specifications of their 14nm process. If Intel fudges their numbers, then they open themselves up to lawsuits.

The information will be eventually posted at IEDM 2014. Conferences like IEDM and the VLSI Symposium are not about marketing - they're about science. Consider this to be a preview for those events.

You mean like the last 10+ years of people tooing and froing on forums saying the same thing and get massively overexcited every time? Companies have been releasing tech specs for years.

Every company goes on and on how their xyz tech is better than their competitor's xyz tech and hardware enthusiasts on forums and the general tech press get overexcited making grandiose predictions.

It happened last time when 22NM finfets was released(competition is doomed according to some people) and charts from Intel came up and the same when the competition released their tech before that (Intel is doomed according to some people since it costs sooooo much less than Intel and its more denser).

The same thing is happening here again.

Everytime any fab introduces a new process node we get these same arguments. Everytime people hype and get overexcited. Most of the time it either leads to intense disappointment or people moving the goalposts to the the next cycle and so on.

Its happened everytime companies like Intel,TSMC,Samsung,GF,etc start releasing their PR events regarding process tech. Its been happening for years on tech forums.

Rinse and repeat.

I have to agree with frozentundra123456 about this - I am more worried about the products and how good they are.

I am far more interested in seeing how Broadwell and Skylake turn out,rather than all these cyclic arguments about process node technology which have been happening for over 10 years on forums. Unless you can make identical products on multiple nodes to compare,its a moot point on which is "better" or "worse" since you ignoring the impact of the other aspects of the design process too. Look at graphics cards made on the same process nodes even.

I am sure it will not put to rest the debate about which process is better. Intel fans will claim it proves how far ahead they are, and intel haters will argue that is it only public relations BS.

Personally, I dont really care about any of the arguments about how dense 14 nm is, or how Samsung's, et. al. processes compare, etc.

Just get the damn chips out and lets see some benchmarks and power consumption figures.

 

[Arachnotronic]

Is 52nm for T1 or T2 ??? because at 22nm T1 is 90nm not 80nm.

Good catch. 22nm was indeed 90nm at M1 and 80nm for M2-M6 (depending on your design).

We'll probably get full(er) details at IDF 2014.

 

[witeken]

What are Idontcare's thoughts on Intel's 14nm?


It seems Intel didn't disclose 14nm gate length.

 

[raghu78]

Intel's slides were compared to TSMC, not Samsung. AFAIK, all Intel's mobile competitors will use TSMC's process, which had a lower density than Samsung's process.

then you don't know anything :biggrin:

http://www.reuters.com/article/2014/07/17/tsmc-orders-idUSL4N0PS0VK20140717

Samsung's process is about the same as FF+. Intel was traditionally behind in density at every node, and now Intel is ahead by a nice margin that will be reduced by FF+, whenever that launches; in ~H2'16, I'd geuss. Intel is boasting a 2X efficiency improvement, on top of the 2X improvement Intel already got with 22nm. So Intel really is a lot ahead in area, power and TTM, about 3-4 years I'd say.

only in your dreams. TTM lead is a year. 16FF+ matches Intel 14nm in transistor performance while being marginally behind in transistor density.

http://www.tsmc.com/uploadfile/ir/quarterly/2014/1aT1b/E/TSMC%201Q14%20transcript.pdf

"16 FinFET plus matches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today.Compared to our own 20 SoC, 16 FinFET plus offers 40% speed improvement. The design rules of 16 FinFET and 16 FinFET plus are the same; IPs are compatible. "


http://electronics360.globalspec.com/article/3974/tsmc-tweaks-16nm-finfet-to-match-intel

Currently 16-FinFET SRAM yield is already close to 20SoC. And with this status we are developing an enhanced transistor version of 16-FinFET plus, with 15 percent performance improvement. It will be the highest performance technology among all available 16 and 14nm technology in 2014," said Co-CEO Mark Liu. He added that back-end design rules would be similar to 16nm FinFET but that there would also be opportunities to use the Plus transistor to reduce standard cell size and therefore reduce chip size. Liu said that the 16nm FinFET Plus would match the performance of Intel's 16nm FinFET process. "So from our intelligence, our 16-FinFET plus technology with 15 percent improvement on top of 16-FinFET is about the same as Intel's transistors," he said.

http://www.cadence.com/Community/bl...-ahead-for-16nm-finfet-plus-10nm-and-7nm.aspx

Hou said that TSMC was able to improve power, performance, and area in this "second generation" FinFET technology for four reasons:

• Learning from 20SoC production has allowed for better process control, and as a result, signoff corners have been tightened so as to reduce the need for over-design
• Device enhancement
• Middle end of line (MEOL) improvements
• Back end of line (BEOL) improvements

Combine all these factors, Hou said, and a 16FF+ ring oscillator simulation will show a 20% to 23% speed improvement compared to 16FF. More specifically, standard cells show a 16% to 18% speed improvement, memory shows a 17%-19% speed improvement, eFUSE shows a 13% speed improvement, and I/O devices provide a 3% speed improvement. However, the 16FF+ technology significantly reduces I/O device leakage.

http://www.tsmc.com/uploadfile/ir/quarterly/2014/2YN1J/E/TSMC 2Q14 transcript.pdf

page 4

"The 16-nanometer development leverages off 20-SoC learning and is moving forward smoothly. Our 16-nanometer is more than competitive, combining performance, density and yields considerations. 16-nanometer applications cover a wide range including baseband, application processors, consumer SoCs, GPU, network processors, hard disk drive, FPGA, servers and CPUs. Volume production of 16-nanometer is expected to begin in late 2015 and there will be a fast ramp up in 2016. The ecosystem for 16-nanometer designs is current and ready."

 

[witeken]

Slide 29-33 for Intel's updated infamous slide. Now less ambiguous.

 

[Arachnotronic]

@ raghu78

The only published specifications of a TSMC 16 FinFET process claim a 90nm gate pitch, 64nm minimum metal, and 0.07um^2 SRAM cell size.

This is not competitive with what Intel has just published. Samsung's 14nm is much more competitive on paper (78nm gate pitch, 64nm minimum metal, and 0.064um^2 SRAM cell size), but given that Samsung's 20nm process went really badly, it's hard to imagine that it's just going to go into HVM on 14nm without any problems.

Intel just demonstrated a very impressive 14-nanometer process, complete with products to boot. While others are close "in PR" let's see if they're actually close in terms of product time to market and, more importantly, yields.

 

[witeken]

Don't forget power consumption.

 

[Phynaz]

16 FinFET plus matches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today.

The devil is in the details.

That's dated April April 17th, 2014. Was Intel's 14mn technology "available in the market" at that time? What do they even mean by available?

 

[raghu78]

@ raghu78

The only published specifications of a TSMC 16 FinFET process claim a 90nm gate pitch, 64nm minimum metal, and 0.07um^2 SRAM cell size.

This is not competitive with what Intel has just published. Samsung's 14nm is much more competitive on paper (78nm gate pitch, 64nm minimum metal, and 0.064um^2 SRAM cell size), but given that Samsung's 20nm process went really badly, it's hard to imagine that it's just going to go into HVM on 14nm without any problems.

Intel just demonstrated a very impressive 14-nanometer process, complete with products to boot. While others are close "in PR" let's see if they're actually close in terms of product time to market and, more importantly, yields.

yeah i agree on Intel's TTM lead. roughly 6 months ahead of Samsung and 9 - 12 months ahead of TSMC 16FF/16FF+. But only a naive person would underestimate TSMC. TSMC will prove by next year end that they can ramp a highly competitive 16FF+ process with good yields (though not as good as Intel).

 

[raghu78]

The devil is in the details.

That's dated April April 17th, 2014. Was Intel's 14mn technology "available in the market" at that time? What do they even mean by available?

come on. don't kid me. You know as well that TSMC was talking about Intel and Samsung .

 

[Arachnotronic]

yeah i agree on Intel's TTM lead. roughly 6 months ahead of Samsung and 9 - 12 months ahead of TSMC 16FF/16FF+. But only a naive person would underestimate TSMC. TSMC will prove by next year end that they can ramp a highly competitive 16FF+ process with good yields (though not as good as Intel).

Do you truly believe that after Samsung was *later* to market at 28nm and seemingly botched 20nm that 14nm is going to be a cakewalk?

Realistically, what's going on with Samsung is that its mobile devices business is seeing profitability plummet (commodity Android phones is what Samsung sells, so why should it be able to sustain Apple-like profitability?) and it recognizes that the best way to keep investors happy and to drive a more sustainable long-term business is to try to hype itself up as a TSMC-killer.

Problem is, TSMC's track record -- as much as everybody gives them crap -- is still far better as a foundry than Samsung's is from what I can tell.

I'll believe Samsung will go into Intel-like HVM production in "6 months" when I see it.

 

[Fjodor2001]

http://www.intc.com/eventdetail.cfm?eventid=149021

The endless debates about TSMC/Samsung/Intel 16/14nm density, performance, and power will be put to rest on August 11.

So what's the conclusion - is Intel 14 nm 35% more dense than TSMC 16FF+ and Samsung 14 nm as Intel claimed earlier at the investors meeting?

 

[ShintaiDK]

Samsung already announced their 14nm only got 14% less scaling than their buthered 20nm.

And TSMC, they are just on 20nm planar with questionable yields and prices through the roof. Specially 16nm FF+ got a long way to go before we see that.

All this while Intel is shipping second generation finfets on 14nm today with high yield. And showing products with huge benefits in all parameters.

And Samsung in its slides says there is no transistor cost reduction at 20nm and down. The same also applies to TSMC. While Intel shows a huge drop in transistor cost at 14nm. Thats the real gamechanger.

 

[Hans de Vries]

Intel's Mark Bohr claimed that logic density could be approximated by minimum metal pitch * contacted gate pitch, and on that metric, Intel is quite a bit ahead.

By this metric the actual logic density scaling would be 80/52 * 90/70 = 1.98 x

 

[witeken]

By this metric the actual logic density scaling would be 80/52 * 90/70 = 1.98 x

Which is what Intel is claiming (0.51x).

 

[Exophase]

Which is what Intel is claiming (0.51x).

So not "2.36x instead of 2.2x"? (or, 0.42x instead of 0.45x)

 

[witeken]

So not "2.36x instead of 2.2x"? (or, 0.42x instead of 0.45x)

The density is not determined by 1 metric. Although density scaling is lower than I anticipated, Intel did scale the minimum pitch more than usual, which was probably what that investor meeting slide was referring to.

 

[mavere]

So what's the conclusion - is Intel 14 nm 35% more dense than TSMC 16FF+ and Samsung 14 nm as Intel claimed earlier at the investors meeting?

Intel's old numbers were based on TSMC's vanilla 16FF, not 16FF+.

Based on the published SRAM size, Intel's 14nm is ~10% denser than Samsung's 14nm. I'm guessing that TSMC's 16FF+ numbers would be equal to or "only" slightly worse than Samsung's.

 

[Exophase]

The density is not determined by 1 metric. Although density scaling is lower than I anticipated, Intel did scale the minimum pitch more than usual, which was probably what that investor meeting slide was referring to.

If that's what they used for the slides it wasn't a good metric. This was long after Intel taped out Broadwell, meaning they should have had a good sense for what the scaling was for an actual shrink of complicated logic. Or at the very least they could have used this rule of thumb Mark Bohr thinks is a good approximation of design scaling, and not just the most favorable metric.

 

[witeken]

The resolution capability of a system - the minimum feature that can be printed - is described by the Rayleigh equation:

Resolution = k1 Lamda / NA

A larger k1 factor means that the lithographic process control is easier and the yield is higher. Usually, a k1 factor above 0.30 is needed for production and k1 cannot typically go below 0.25. A lithographic process in which 0.25 < k1 < 0.30 is difficult and requires very aggressive resolution enhancement techniques.

Using a 193i immersion tool with NA = 1.35, a 80nm pitch requires a k1 factor that is less than 0.30.

Regardless of transistor choice, whether bulk planar, FD-SOI, or FinFET, each transistors need three contacts and routing metals. This is why the metal 1 pitch is important since the transistors are dwarfed by the metal 1 layer. With FinFET devices, the fin pitch becomes the dominant factor for SRAM layout:



http://vlsicad.ucsd.edu/Publications/Conferences/302/c302.pdf

The Intel 14nm node appears to be a node shrink of their 22nm node. However, I think the most important question is weather the Intel SRAM design is continuing to sit on the usual area scaling trend.

1D gridded layouts provide better overlay between M1 and M2 layers, and SADP has better OPC than LELE. Nevertheless, there are some results showing that the operating voltage do not scale in the same proportion as the logic devices on the same die. As such, the fundamental trade off is between cell stability and area.

An SRAM cell size smaller than 0.05µm2 will be impressive. But, I would not be surprised if their memory design is not sitting on the area scaling trend.

It's 16% larger than 0.05µm.

 

[Fjodor2001]

Intel's old numbers were based on TSMC's vanilla 16FF, not 16FF+.

Based on the published SRAM size, Intel's 14nm is ~10% denser than Samsung's 14nm. I'm guessing that TSMC's 16FF+ numbers would be equal to or "only" slightly worse than Samsung's.

So in short, Intel provided incorrect information in this slide:

 

[Khato]

So in short, Intel provided incorrect information in this slide

I don't see anything on that slide stating that it's comparing SRAM density. After all, that's merely one metric of process density.

 

[witeken]

So in short, Intel provided incorrect information in this slide:

No they didn't (they used sources from TSMC). But the slide is ambiguous. Also, we don't know when FF+ will launch in products.

 

[antihelten]

No they didn't (they used sources from TSMC). But the slide is ambiguous. Also, we don't know when FF+ will launch in products.

Technically they used sources from TSMC for 16FF, and sources from the IBM alliance for 28nm, 20nm and 10nm, at least if the new slides you linked to previously are to be trusted.