No they didn't (they used sources from TSMC). But the slide is ambiguous. Also, we don't know when FF+ will launch in products.
Normally SRAM size is used as standard measurement for density. Yes there can be other ways of measuring it, but this is the default unless something else is explicitly stated. And Intel did not make any such other explicit statement saying otherwise.
The slide says Intel's 14 nm is 35% more dense than TSMC 16FF / Samsung 14 nm. Now the actual data show SRAM is only ~10% more dense on 14 nm using Intel's process. I.e. the info they provided was incorrect.
And TSMC, they are just on 20nm planar with questionable yields and prices through the roof. Specially 16nm FF+ got a long way to go before we see that.
All this while Intel is shipping second generation finfets on 14nm today with high yield. And showing products with huge benefits in all parameters.
And Samsung in its slides says there is no transistor cost reduction at 20nm and down. The same also applies to TSMC. While Intel shows a huge drop in transistor cost at 14nm. Thats the real gamechanger.
The contacted gate pitch is the key metric for area scaling. On that metric Intel 14nm at 70nm is 10% lesser than Samsung 14nm at 78nm. On SRAM cell size the lead is just above 8%. Intel's claims of foundries process being 20nm with FINFET is pure rubbish. if what Intel claims is true then their own process is more like a 18nm FINFET process. :biggrin:
Intel has always had a lower density at the same node, that was compensated with a much higher (1 node) performance and power lead and a 1 node TTM lead. Now Intel is actually catching up and its density per node won't be worse anymore, while also increasing its lead in power, performance and TTM (TSMC's 10nm will have higher density, but possibly not by as much as 22nm vs 28nm, and it will be 3-4 years later than Intel).
BTW, for the end consumer, density doesn't even matter at all. It's price per transistor that matters, and while that metric is getting lower at constant speed, TSMC's and Samsung's P/T has bottomed since 28nm. So effectively, Intel also has a 5+ year density lead.
Sure, I change my opinions to reality as I get more information, instead of holding on to a reality that does no exist, like many people do...So now that you realize Intel's statement claiming 35% density advantage on 14 nm was BS, you:
There's nothing more to say about the graph than I already did.* Try to move the discussion to other areas.
I will not argue with this stupid argument because I don't remember everything I said, but I think you are just putting words in my mouth that aren't mine.* Say that density is not so important after all (in previous discussions you mentioned how Intel's density advantage on 14 nm was going to be a huge benefit for them).
If you look at that slide, you see that Intel also made a claim about 10nm.* Start speculating about 10 nm instead.
I rest my case... :biggrin:
Intel has always had a lower density at the same node.
performance lead and TTM lead at 22nm FINFET was undeniable.that was compensated with a much higher (1 node) performance and power lead and a 1 node TTM lead.
TSMC 16FF+ is on par with Intel 14nm in performance and marginally behind in transistor density. TSMC is 1 yr behind Intel 14nm in TTM.Now Intel is actually catching up and its density per node won't be worse anymore, while also increasing its lead in power, performance and TTM (TSMC's 10nm will have higher density, but possibly not by as much as 22nm vs 28nm, and it will be 3-4 years later than Intel).
You still repeat like a Intel PR mouthpiece. I don't take Intel's transistor cost claims on face value just like their so called "35% density advantage claims" over foundries 16/14 FINFET. lets see how actual products fare in marketplace.BTW, for the end consumer, density doesn't even matter at all. It's price per transistor that matters, and while that metric is getting lower at constant speed, TSMC's and Samsung's P/T has bottomed since 28nm. So effectively, Intel also has a 5+ year density lead. Let's see what happens to your grinning smileys in the coming years .
That's exactly what I said. Lower density means fewer transistors per mm², which is true considering that 22nm is below the half-node 28nm.wrong. Intel's 22nm contacted gate pitch was 90nm for high performance , standard performance and low power process. for ultra low power process the contacted gate pitch was 108nm. this ultra low power might be what baytrail used and this explains why baytrail never was significantly smaller than A7 in die size for a roughly similar transistor count of 1 billion transistors.
http://electroiq.com/chipworks_real_chips_blog/page/2/
(figure 1)
Samsung 28nm contacted gate pitch was 120nm.
http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/
"The A7 is Apples first 28 nm device. The process technology is broadly similar to that used at 32 nm, with an ~10% shrink of the contacted gate pitch to 120 nm."
Source? 14nm is Intel's second generation Tri-Gate, which doubles efficiency. TSMC's FinFET does the same compared to their 2nd gen HKMH. Intel's 2nd gen HKMG was 32nm, 4 years ago.TSMC 16FF+ is on par with Intel 14nm in performance and marginally behind in transistor density.
Intel has never compared cost per transistor. ARM, Nvidia and Samsung have done that however.You still repeat like a Intel PR mouthpiece. I don't take Intel's transistor cost claims on face value just like their so called "35% density advantage claims" over foundries 16/14 FINFET. lets see how actual products fare in marketplace.
Really looking forward to Core M and Broxton versus its competition as well. And if Apple or some other company shares its transistor count, we'll also be able to get some nice facts about end-product density.Cherrytrail vs A8 vs S810
Broxton vs A9 vs FinFET snapdragon.
In fact I am looking forward to A9 vs Core M as I am pretty sure Apple has some serious performance upgrades coming for their first FINFET SOC.
Source? 14nm is Intel's second generation Tri-Gate, which doubles efficiency. TSMC's FinFET does the same compared to their 2nd gen HKMH. Intel's 2nd gen HKMG was 32nm, 4 years ago.
yeah same hereReally looking forward to Core M and Broxton versus its competition as well. And if Apple or some other company shares its transistor count, we'll also be able to get some nice facts about end-product density.
I don't think TSMC has access to Intel's 14nm process, so let's wait for actual products, or maybe someone with more process knowledge can comment."So from our intelligence, our 16-FinFET plus technology with 15 percent improvement on top of 16-FinFET is about the same as Intel's transistors," he said.
The contacted gate pitch is the key metric for area scaling. On that metric Intel 14nm at 70nm is 10% lesser than Samsung 14nm at 78nm. On SRAM cell size the lead is just above 8%. Intel's claims of foundries process being 20nm with FINFET is pure rubbish. if what Intel claims is true then their own process is more like a 18nm FINFET process. :biggrin:
Copmany: (gate pitch) x (metal pitch)
Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²
FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.
So it seems nothing changed and Intel still has this ~35% smaller area per transistor?
No, you're calculating the density advantage of Intel wrong. Intel is almost 40% ahead of Samsung in terms of transistors per area.Intel's 14nm is ~36% denser than TSMC's 16/20nm processes by this metric, and 27% denser than Samsung's 14nm.
Mark Bohr explained this measure in one of their slides and the webcast.By this metric that Intel clearly defined, Intel meets the claims that it set out previously. Whether this is the best measure, that's up to the viewer.
Normally SRAM size is used as standard measurement for density. Yes there can be other ways of measuring it, but this is the default unless something else is explicitly stated. And Intel did not make any such other explicit statement saying otherwise.
TSMC 16FF+ is on par with Intel 14nm in performance and marginally behind in transistor density.
come on. don't kid me. You know as well that TSMC was talking about Intel and Samsung .
Playing the numbers game by taking a rough approximation for one process (with a lot of unknowns to even get that approximation) as an universal rule for the industry is a terrible idea. You might as well add a confidence interval of [greater than your calculated difference].Company: (gate pitch) x (metal pitch)
Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²
Intel 22: 90nm x 80nm = 7.200nm²
FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.
So it seems nothing changed and Intel still has this ~35% smaller area per transistor?
Company: (gate pitch) x (metal pitch)
Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²
Intel 22: 90nm x 80nm = 7.200nm²
FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.
So it seems nothing changed and Intel still has this ~35% smaller area per transistor?