Intel to Detail 14nm Process on August 11

[witeken]

I was talking about the investor meeting slide. The new slide has different sources.

 

[Fjodor2001]

No they didn't (they used sources from TSMC). But the slide is ambiguous. Also, we don't know when FF+ will launch in products.

Normally SRAM size is used as standard measurement for density. Yes there can be other ways of measuring it, but this is the default unless something else is explicitly stated. And Intel did not make any such other explicit statement saying otherwise.

The slide says Intel's 14 nm is 35% more dense than TSMC 16FF / Samsung 14 nm. Now the actual data show SRAM is only ~10% more dense on 14 nm using Intel's process. I.e. the info they provided was incorrect.

 

[raghu78]

Normally SRAM size is used as standard measurement for density. Yes there can be other ways of measuring it, but this is the default unless something else is explicitly stated. And Intel did not make any such other explicit statement saying otherwise.

The slide says Intel's 14 nm is 35% more dense than TSMC 16FF / Samsung 14 nm. Now the actual data show SRAM is only ~10% more dense on 14 nm using Intel's process. I.e. the info they provided was incorrect.

The contacted gate pitch is the key metric for area scaling. On that metric Intel 14nm at 70nm is 10% lesser than Samsung 14nm at 78nm. On SRAM cell size the lead is just above 8%. Intel's claims of foundries process being 20nm with FINFET is pure rubbish. if what Intel claims is true then their own process is more like a 18nm FINFET process. :biggrin:

 

[raghu78]

And TSMC, they are just on 20nm planar with questionable yields and prices through the roof. Specially 16nm FF+ got a long way to go before we see that.

All this while Intel is shipping second generation finfets on 14nm today with high yield. And showing products with huge benefits in all parameters.

You talk as if you know the exact yields and wafer prices at TSMC 20nm and Intel 14nm . stop talking rubbish.

And Samsung in its slides says there is no transistor cost reduction at 20nm and down. The same also applies to TSMC. While Intel shows a huge drop in transistor cost at 14nm. Thats the real gamechanger.

yeah real game changer. just like intel said they are 35% denser than foundries 16/14nm.

 

[witeken]

The contacted gate pitch is the key metric for area scaling. On that metric Intel 14nm at 70nm is 10% lesser than Samsung 14nm at 78nm. On SRAM cell size the lead is just above 8%. Intel's claims of foundries process being 20nm with FINFET is pure rubbish. if what Intel claims is true then their own process is more like a 18nm FINFET process. :biggrin:

Intel has always had a lower density at the same node, that was compensated with a much higher (1 node) performance and power lead and a 1 node TTM lead. Now Intel is actually catching up and its density per node won't be worse anymore, while also increasing its lead in power, performance and TTM (TSMC's 10nm will have higher density, but possibly not by as much as 22nm vs 28nm, and it will be 3-4 years later than Intel).

BTW, for the end consumer, density doesn't even matter at all. It's price per transistor that matters, and while that metric is getting lower at constant speed, TSMC's and Samsung's P/T has bottomed since 28nm. So effectively, Intel also has a 5+ year density lead. Let's see what happens to your grinning smileys in the coming years .

 

[Fjodor2001]

Intel has always had a lower density at the same node, that was compensated with a much higher (1 node) performance and power lead and a 1 node TTM lead. Now Intel is actually catching up and its density per node won't be worse anymore, while also increasing its lead in power, performance and TTM (TSMC's 10nm will have higher density, but possibly not by as much as 22nm vs 28nm, and it will be 3-4 years later than Intel).

BTW, for the end consumer, density doesn't even matter at all. It's price per transistor that matters, and while that metric is getting lower at constant speed, TSMC's and Samsung's P/T has bottomed since 28nm. So effectively, Intel also has a 5+ year density lead.

So now that you realize Intel's statement claiming 35% density advantage on 14 nm was BS, you:

* Try to move the discussion to other areas.
* Say that density is not so important after all (in previous discussions you mentioned how Intel's density advantage on 14 nm was going to be a huge benefit for them).
* Start speculating about 10 nm instead.

I rest my case... :biggrin:

 

[witeken]

So now that you realize Intel's statement claiming 35% density advantage on 14 nm was BS, you:

Sure, I change my opinions to reality as I get more information, instead of holding on to a reality that does no exist, like many people do...

BTW, I didn't really use this graph to claim such a density lead, but to more generally state that the foundries are falling behind. It's less than I expected but nonetheless it's true.

* Try to move the discussion to other areas.

There's nothing more to say about the graph than I already did.

* Say that density is not so important after all (in previous discussions you mentioned how Intel's density advantage on 14 nm was going to be a huge benefit for them).

I will not argue with this stupid argument because I don't remember everything I said, but I think you are just putting words in my mouth that aren't mine.

* Start speculating about 10 nm instead.

If you look at that slide, you see that Intel also made a claim about 10nm.

I rest my case... :biggrin:

I suppose it's now my turn? You saw that my claims of TSMC and Samsung falling behind are painfully right, but instead you choose to reply to my post with an argumentum ad hominem fallacy. So please stop the smileys and post some constructive posts. Until then, I rest my case.

 

[raghu78]

Intel has always had a lower density at the same node.

wrong. Intel's 22nm contacted gate pitch was 90nm for high performance , standard performance and low power process. for ultra low power process the contacted gate pitch was 108nm. this ultra low power might be what baytrail used and this explains why baytrail never was significantly smaller than A7 in die size for a roughly similar transistor count of 1 billion transistors.

http://electroiq.com/chipworks_real_chips_blog/page/2/

(figure 1)

Samsung 28nm contacted gate pitch was 120nm.

http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/

"The A7 is Apple’s first 28 nm device. The process technology is broadly similar to that used at 32 nm, with an ~10% shrink of the contacted gate pitch to 120 nm."

that was compensated with a much higher (1 node) performance and power lead and a 1 node TTM lead.

performance lead and TTM lead at 22nm FINFET was undeniable.

Now Intel is actually catching up and its density per node won't be worse anymore, while also increasing its lead in power, performance and TTM (TSMC's 10nm will have higher density, but possibly not by as much as 22nm vs 28nm, and it will be 3-4 years later than Intel).

TSMC 16FF+ is on par with Intel 14nm in performance and marginally behind in transistor density. TSMC is 1 yr behind Intel 14nm in TTM.

BTW, for the end consumer, density doesn't even matter at all. It's price per transistor that matters, and while that metric is getting lower at constant speed, TSMC's and Samsung's P/T has bottomed since 28nm. So effectively, Intel also has a 5+ year density lead. Let's see what happens to your grinning smileys in the coming years .

You still repeat like a Intel PR mouthpiece. I don't take Intel's transistor cost claims on face value just like their so called "35% density advantage claims" over foundries 16/14 FINFET. lets see how actual products fare in marketplace.

Cherrytrail vs A8 vs S810
Broxton vs A9 vs FinFET snapdragon.

In fact I am looking forward to A9 vs Core M as I am pretty sure Apple has some serious performance upgrades coming for their first FINFET SOC.

 

[witeken]

wrong. Intel's 22nm contacted gate pitch was 90nm for high performance , standard performance and low power process. for ultra low power process the contacted gate pitch was 108nm. this ultra low power might be what baytrail used and this explains why baytrail never was significantly smaller than A7 in die size for a roughly similar transistor count of 1 billion transistors.

http://electroiq.com/chipworks_real_chips_blog/page/2/

(figure 1)

Samsung 28nm contacted gate pitch was 120nm.

http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/samsung-28-nm-apple-a7/

"The A7 is Apple’s first 28 nm device. The process technology is broadly similar to that used at 32 nm, with an ~10% shrink of the contacted gate pitch to 120 nm."

That's exactly what I said. Lower density means fewer transistors per mm², which is true considering that 22nm is below the half-node 28nm.

TSMC 16FF+ is on par with Intel 14nm in performance and marginally behind in transistor density.

Source? 14nm is Intel's second generation Tri-Gate, which doubles efficiency. TSMC's FinFET does the same compared to their 2nd gen HKMH. Intel's 2nd gen HKMG was 32nm, 4 years ago.

You still repeat like a Intel PR mouthpiece. I don't take Intel's transistor cost claims on face value just like their so called "35% density advantage claims" over foundries 16/14 FINFET. lets see how actual products fare in marketplace.

Intel has never compared cost per transistor. ARM, Nvidia and Samsung have done that however.

Cherrytrail vs A8 vs S810
Broxton vs A9 vs FinFET snapdragon.

In fact I am looking forward to A9 vs Core M as I am pretty sure Apple has some serious performance upgrades coming for their first FINFET SOC.

Really looking forward to Core M and Broxton versus its competition as well. And if Apple or some other company shares its transistor count, we'll also be able to get some nice facts about end-product density.

 

[raghu78]

Source? 14nm is Intel's second generation Tri-Gate, which doubles efficiency. TSMC's FinFET does the same compared to their 2nd gen HKMH. Intel's 2nd gen HKMG was 32nm, 4 years ago.

Actually TSMC developed 16FF+ based on their learning with 20SOC/16FF. TSMC wanted to remain competitive with Intel 14nm and Samsung 14nm on power, performance and area.

http://www.cadence.com/Community/bl...-ahead-for-16nm-finfet-plus-10nm-and-7nm.aspx

"The 16FF and 16FF+ technologies are "ready for prime time," according to Sun (left). He noted that the 16FF yield has already caught up with the 20nm planar (20SoC) process node. As a second-generation FinFET technology, he said, 16FF+ can provide an additional 15% die size reduction compared to 20SoC.


"Hou said that TSMC was able to improve power, performance, and area in this "second generation" FinFET technology for four reasons:

• Learning from 20SoC production has allowed for better process control, and as a result, signoff corners have been tightened so as to reduce the need for over-design
• Device enhancement
• Middle end of line (MEOL) improvements
• Back end of line (BEOL) improvements

Combine all these factors, Hou said, and a 16FF+ ring oscillator simulation will show a 20% to 23% speed improvement compared to 16FF. More specifically, standard cells show a 16% to 18% speed improvement, memory shows a 17%-19% speed improvement, eFUSE shows a 13% speed improvement, and I/O devices provide a 3% speed improvement. However, the 16FF+ technology significantly reduces I/O device leakage."


http://electronics360.globalspec.com/article/3974/tsmc-tweaks-16nm-finfet-to-match-intel

"Currently 16-FinFET SRAM yield is already close to 20SoC. And with this status we are developing an enhanced transistor version of 16-FinFET plus, with 15 percent performance improvement. It will be the highest performance technology among all available 16 and 14nm technology in 2014," said Co-CEO Mark Liu. He added that back-end design rules would be similar to 16nm FinFET but that there would also be opportunities to use the Plus transistor to reduce standard cell size and therefore reduce chip size. Liu said that the 16nm FinFET Plus would match the performance of Intel's 16nm FinFET process. "So from our intelligence, our 16-FinFET plus technology with 15 percent improvement on top of 16-FinFET is about the same as Intel's transistors," he said.

http://www.tsmc.com/uploadfile/ir/quarterly/2014/1aT1b/E/TSMC 1Q14 transcript.pdf

(page 4)

"Then I cover the updates on 16 FinFET, 16 FinFET plus and our 10 FinFET. First, we have two general offers for customers, 16 FinFET and 16 FinFET plus. 16 FinFET plus offers 15% speed improvement, the same total power, compared to 16 FinFET. More importantly, 16 FinFET plus offers 30% total power reduction at the same speed, compared to 16 FinFET. Our 16 FinFET plus matches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today. Compared to our own 20 SoC, 16 FinFET plus offers 40% speed improvement. The design rules of 16 FinFET and 16 FinFET plus are the same; IPs are compatible"

http://www.eda.org/edps/edp2013/Papers/4-4 FINAL for Tom Quan.pdf

page 19

performance at same power
28HPM - 1x
20SOC - 1.15x
16FF - 1.38x (1.15x * 1.2 = 1.38x) or 20% improvement wrt 20 SOC
16FF+ - 1.59x (1.38x * 1.15 = 1.587x) or roughly 60% improvement wrt 28HPM
(1.15x * 1.38 = 1.587x) or close to 40% improvement wrt 20 SOC

Really looking forward to Core M and Broxton versus its competition as well. And if Apple or some other company shares its transistor count, we'll also be able to get some nice facts about end-product density.

yeah same here

 

[witeken]

Some people are expecting that Intel will be only ~10% ahead. When I look at slide 31, however, I see that in Intel's updated information (without forecast this time), they are still quite a lot ahead of others' (regular) FinFET. In this slide however they are unambiguously using 2 published metrics to determine SRAM density: gate pitch x metal pitch. So what's up with that slide, is it wrong?

 

[witeken]

"So from our intelligence, our 16-FinFET plus technology with 15 percent improvement on top of 16-FinFET is about the same as Intel's transistors," he said.

I don't think TSMC has access to Intel's 14nm process, so let's wait for actual products, or maybe someone with more process knowledge can comment.

 

[Arachnotronic]

The contacted gate pitch is the key metric for area scaling. On that metric Intel 14nm at 70nm is 10% lesser than Samsung 14nm at 78nm. On SRAM cell size the lead is just above 8%. Intel's claims of foundries process being 20nm with FINFET is pure rubbish. if what Intel claims is true then their own process is more like a 18nm FINFET process. :biggrin:

So, metal pitch (i.e. BEOL) is irrelevant to area scaling?

That's news to me.

 

[witeken]

Company: (gate pitch) x (metal pitch)

Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²
Intel 22: 90nm x 80nm = 7.200nm²

FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.

So it seems nothing changed and Intel still has this ~35% smaller area per transistor?

 

[Arachnotronic]

So, if we want to use Intel's metric for logic density (gate pitch * minimum metal), then we get the following for the various processes:

Samsung 28nm = 114*90nm = 10260
TSMC 20nm - 90nm*64nm = 5760
TSMC 16nm - 90nm*64nm = 5760
Samsung 14nm - 78nm*64nm = 4992
Intel 14nm - 70nm*52nm = 3640
Intel 22nm - 90nm*80nm = 7200

Intel's 14nm is ~36% denser than TSMC's 16/20nm processes by this metric, and 27% denser than Samsung's 14nm.

By this metric that Intel clearly defined, Intel meets the claims that it set out previously. Whether this is the best measure, that's up to the viewer.

 

[Arachnotronic]

Copmany: (gate pitch) x (metal pitch)

Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²

FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.

So it seems nothing changed and Intel still has this ~35% smaller area per transistor?

Heh, you beat me to it.

Do you have a source for the 80nm gate pitch for FinFET+, though?

 

[witeken]

Sorry, the "TSMC" and "FF Plus" nodes I mentioned are not TSMC's, although they should be close. I was searching for information about TSMC's nodes, but couldn't find so I toke IBM's data:

https://www.semiwiki.com/forum/content/1789-16nm-finfet-versus-20nm-planar.html

 

[witeken]

Intel's 14nm is ~36% denser than TSMC's 16/20nm processes by this metric, and 27% denser than Samsung's 14nm.

No, you're calculating the density advantage of Intel wrong. Intel is almost 40% ahead of Samsung in terms of transistors per area.

What you calculated is how much smaller Intel's transistors are. So if Samsung is 100, Intel would be (100-27=) 73. If Intel is 100 (area), Samsung would be 137 (area).

By this metric that Intel clearly defined, Intel meets the claims that it set out previously. Whether this is the best measure, that's up to the viewer.

Mark Bohr explained this measure in one of their slides and the webcast.

 

[Space69]

Normally SRAM size is used as standard measurement for density. Yes there can be other ways of measuring it, but this is the default unless something else is explicitly stated. And Intel did not make any such other explicit statement saying otherwise.

A rough estimate of logic (not SRAM cells) density is derived from (Mark Bohr Senior Intel fellow) :

Gate pitch * Metal/Interconnect pitch

Public stated dimensions :

Intel (http://images.anandtech.com/doci/8367/14nmFeatureSize.png)

Fin pitch : 42nm
Gate pitch : 70 nm
Metal/Interconnect pitch : 52 nm

TSMC (http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6724591&punumber%3D6709840%26sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6724533%29%26pageNumber%3D3) Under Process Architecture page 224

Fin pitch : 48nm
Gate pitch : 90 nm
Metal/Interconnect pitch : 64nm

http://images.anandtech.com/doci/8367/14nmScaling.png

Edit: Witeken/Intel17 beats me to it regarding the calculations.

So Intel DID explicitly stated how they arrived to the numbers.

 

[dawheat]

I thought TSMC's volume production at 20nm started several months ago with Apple. Is it really realistic to believe that their 16FF AND 16FF+ will be in volume production next year? I want competition in this space as much as anyone, but it doesn't seem to pass the sniff test.

 

[witeken]

It is realistic because it is not a totally new process, only the FinFET transistor is new. So production in 2015 is possible, but products not.

 

[Khato]

TSMC 16FF+ is on par with Intel 14nm in performance and marginally behind in transistor density.

Rather than continue the tiresome tirade on density where we now have all of the facts I'd like to hear some informed speculation regarding the performance claim. With all of Intel's disclosures the only two pieces regarding transistor performance that I recall seeing were a reduction in capacitance of at least 0.75x (0.65x for the Broadwell-Y process flavor) and an implication (the slide that went from 3 22nm fins to 2 14nm fins) that the second generation finFET had a markedly higher drive current, possibly around 1.5x.

Now there's no question that the combination of a taller, more rectangular and thinner fin will result in both an increase in drive current and decrease in leakage current. Their stated increase from 34nm to 42nm on fin height should basically represent a corresponding ~25% increase in drive current. The more rectangular and thinner part of the changes is more difficult to quantify, from what I recall of transistor operation though I'd guess it could easily represent another ~25% boost at low voltage, no? Since the more rectangular and thinner fin should result in inversion layer from each side meeting in the middle and allowing the entire fin to conduct at a lower voltage than on the 22nm process.

Oh, and for those that haven't had enough of the density discussion... guess how the above ties into actual design density for high speed SoCs.

 

[Phynaz]

come on. don't kid me. You know as well that TSMC was talking about Intel and Samsung .

I don't know such a thing. You think you know. Your bias is causing you to imply something that wasn't said.

 

[Piroko]

Company: (gate pitch) x (metal pitch)

Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²
Intel 22: 90nm x 80nm = 7.200nm²

FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.

So it seems nothing changed and Intel still has this ~35% smaller area per transistor?

Playing the numbers game by taking a rough approximation for one process (with a lot of unknowns to even get that approximation) as an universal rule for the industry is a terrible idea. You might as well add a confidence interval of [greater than your calculated difference].

 

[AtenRa]

Company: (gate pitch) x (metal pitch)

Intel: 70nm x 52nm = 3.640nm²
TSMC: 90nm x 64nm = 5.760nm²
FF Plus: 80nm x 64nm = 5.120nm²
Intel 22: 90nm x 80nm = 7.200nm²

FinFET Plus: 12.5% more dense than 16nm.
Intel 14nm: 58% more dense than 16nm.

So it seems nothing changed and Intel still has this ~35% smaller area per transistor?

Intel 22nm = 7200
Intel 14nm = 3640

Intel 14nm = 49,4% smaller than 22nm

So then, Intel's 14nm didn't scale down 2.2 times over 22nm like they communicated using a different slide , but not even 2x according to Intel's own measurements ??

Those process PR wars are the worst ive seen. :thumbsdown: