Why?
Yeah, more details would be nice...Sounds interesting. Vaguely.
Not to sure why Intel/Cray are being so secretive.
Knights Hill is being replaced by essentially a Icelake-SP core with 4 AVX-512 units on it.
... but the article says the cluster is being delayed until 2021, so this would be more Sapphire Rapids. Maybe there is something with Saphhire Rapids they don't want to talk about at this point.
Regardless, I am not 100% sure why they would go into some kind of oddball big.LITTLE-style mashup unless they are veering completely away from add-in card Phi and sticking with the socketed products?
The 2021 date was set when Knights Hill was axed,
Yeah I had seen that from Paul Alcorn on twitter though he didn't delve into what, I guess axed was the wrong word to useThey already do in a sense. Many HPC products feature Xeon Phis for some of them, and regular Xeons for the rest. There's lot more Phis, and the amount of systems doing this reduced with the Knights Landing version, but you get the idea.
There's a reason why Intel decided to beef up the cores significantly for Knights Landing. Even though it was primarily targeted for very parallel code, it was still general purpose enough that it was limited by scalar throughput too. Intel often touted 3x increase in core performance, and some say the original Xeon Phi(Knights Corner) was limited by scalar throughput, and needed a more powerful core.
With Knights Landing, real systems have a hard time getting more than 60% efficiency for Linpack. I think I heard some say the 2-issue decode is a bottleneck. Going to a wider core like Goldmont would help. That's what Knights Hill was supposed to be anyway. Xeon Phi with modified Goldmont cores.
Some allege Knights Hill is still in planning. Surprising I know.
I'm really quite curious to see how Intel execute Lake Field and if it works well with Windows Scheduler... IIRC It's supposedly Icelake Core and 10nm Atom cores, could be interesting for tablest, 2in1s, thin and lights, etc..Apple was the first to use small cores/big cores strategy effectively. Their A11 Bionic does this particularly well. The scheduler in that chip is good enough to make the small cores act as an extension to the big core and work like a physical version of SMT.
Samsung uses this in a rudimentary fashion with the Exynos 9810 SoC. The big cores run at high frequency in single thread.
Intel is behind. Ironic because they were the ones to come up with the idea: https://www.anandtech.com/show/2471
Intel's Lake Field is their version for the consumer side. Concepts like big.little are another tricks in a process/thermal/clock limited world to improve performance beyond normal progression.
Apple was the first to use small cores/big cores strategy effectively. Their A11 Bionic does this particularly well. The scheduler in that chip is good enough to make the small cores act as an extension to the big core and work like a physical version of SMT.
Samsung uses this in a rudimentary fashion with the Exynos 9810 SoC. The big cores run at high frequency in single thread.
Intel is behind. Ironic because they were the ones to come up with the idea: https://www.anandtech.com/show/2471
Intel's Lake Field is their version for the consumer side. Concepts like big.little are another tricks in a process/thermal/clock limited world to improve performance beyond normal progression.
Going to a wider core like Goldmont would help. That's what Knights Hill was supposed to be anyway. Xeon Phi with modified Goldmont cores.
Some allege Knights Hill is still in planning. Surprising I know.
It really makes me wonder who is in charge of future technologies at Intel and why they keep going down dead ends that require massive reworks that themselves often become dead ends just a few years later.
Don't they understand what is needed by certain customers now and in 10 years time?