Interesting dispute brewing between Intel/TSMC

[Nothingness]

Anand has already given the die size of a 2C GT3 die in June: The Haswell Review: Intel Core i7-4770K & i5-4670K Tested -- Die Size and Transistor Count

Yes I linked that above. Anand clearly states 181mm² not the 126mm² mikk estimated, which might change the estimate for Broadwell (see Homeles answer for a possibly fixed estimate).

Wasn't directed at anyone in specific. I'm just surprised that people don't know it.

Even though I read a lot, I have a hard time following everything in particular given the flow of information and rumors surrounding Intel

But yeah, you have pointed out something interesting. mikk's Haswell estimate is off, resulting in an erroneous Broadwell estimate. If we assume he wasn't incorrect about Broadwell being 63.4% of the size of Haswell, that would put Broadwell ULT at 115mm2. That would put a quad core GT3 config at a tad over 150mm2.

Your 115mm² is very close to one of the comments which states 114mm². But mikk insisted on his 80mm² being correct which then doesn't match 63.4% of 181mm².

Ha well, I'll wait for Intel official figures I guess :biggrin:

 

[Khato]

The thing which you're all missing is that the Haswell ULT in that picture is 2C GT2, not 2C GT3. You take the measured 181mm^2 for 2C GT3 and subtract 2 cores and their corresponding L3 at roughly 25mm^2 each and you are basically at the calculated 129mm^2 for the Haswell ULT in that picture.

 

[Homeles]

Yes I linked that above. Anand clearly states 181mm² not the 126mm² mikk estimated, which might change the estimate for Broadwell (see Homeles answer for a possibly fixed estimate).


Even though I read a lot, I have a hard time following everything in particular given the flow of information and rumors surrounding Intel

Your 115mm² is very close to one of the comments which states 114mm². But mikk insisted on his 80mm² being correct which then doesn't match 63.4% of 181mm².

Ha well, I'll wait for Intel official figures I guess :biggrin:

Never mind, see below.

The thing which you're all missing is that the Haswell ULT in that picture is 2C GT2, not 2C GT3. You take the measured 181mm^2 for 2C GT3 and subtract 2 cores and their corresponding L3 at roughly 25mm^2 each and you are basically at the calculated 129mm^2 for the Haswell ULT in that picture.

Ouch, you're right. This is Haswell GT3:

Compare to Haswell pictured here:

 

[witeken]

The thing which you're all missing is that the Haswell ULT in that picture is 2C GT2, not 2C GT3. You take the measured 181mm^2 for 2C GT3 and subtract 2 cores and their corresponding L3 at roughly 25mm^2 each and you are basically at the calculated 129mm^2 for the Haswell ULT in that picture.

129mm²?

*The difference between (quadcore) GT2 and GT3 is 264mm² - 177mm² = 87mm².
*Dualcore ULT GT3 is 181mm².
That means dualcore GT2 is 181mm² - 87mm² = 94mm².
-> Broadwell is 63.4% of dualcore 94mm² GT2 Haswell = 59.60mm².

=> Dualcore GT3 Broadwell is 181mm² / 59.60mm² = 3x smaller than dualcore GT3 Haswell (without taking into account the extra transistors Broadwell probably has)

Is there something wrong with my calculation?

Edit: This would mean that quadcore GT3 Broadwell (i7 5770) would be 264mm² / 3 = 88mm². Broadwell with 14nm Crystalwell would be 264+84 / 3 = 116mm². Add some % more mm² for increased amount of transistors. Not sure if this is right.

 

[know of fence]

They're doing so in order to 'catch up' to Intel in implementing FinFET transistors sooner than they would if they were doing a full node shrink. Even in this latest presentation they're only claiming a 15% density improvement going from 20nm to '16nm', a far cry from the ~36% improvement that the node labels imply. (Not that I'm going to fault them for such seeing as how it's standard practice.) And back before they were trying to market against Intel they were only expecting a 1.1x density increase - page 19 of http://www.eda.org/edps/EDP2013/Papers/4-4 FINAL for Tom Quan.pdf

Depends. I suspect that Intel simply made the 20nm to '16nm' density line for TSMC flat to illustrate the effect while the 35% density advantage is based on TSMC's stated 2x density increase going from 28nm to '16nm'.

Very interesting slides. TSMC expects a massive frequency increase from FINFets, and a small area shrink from 20 to 16ff.
Their 28 to 16nm shrink should be a tripling of density, but they claim it's 2x, hmm. Guessing, since I exhausted all possible explanations, then whatever remains, however impossible must be the truth, which is that the 19 from their FinFET process somehow turned on its head into a 16FF. (9 -@-> 6)
Joking aside, TSMC's projections would make more sense with a 19, and so would the Intel slide, assuming 28nm still had meaning.
Intel's 14nm may as well be 15½nm, at least that's what literal commitment to Moore's Law would imply.

I still like to reiterate that both companies find themselves riding the same area scaling curve. Riding it into the abyss of bad yields, high energy density and increased risk of circuitry failure.
The fact that they chose not to disclose their actual positions on that curve, is unfortunate. It should be possible to determine the corresponding real nano-meter lables, so the surprising thing to me is not that the foundries would lie about it, but that nobody is speaking up and saying, "20 TSMC's nm equals X.X real nanometers and Y.Y Intel nm".

Red and blue lines just connect the dots to illustrate their foundry label.

 

[tarlinian]

It should be possible to determine the corresponding real nano-meter lables, so the surprising thing to me is not that the foundries would lie about it, but that nobody is speaking up and saying, "20 TSMC's nm equals X.X real nanometers and Y.Y Intel nm".

That's pretty meaningless. There is nothing in the 22 nm node that's 22 nm. The node labels from a given company once used to indicate that the relative amount of scaling between the products. This has continued to hold true, especially if you look at the SRAM cell. Everyone's SRAM cell has thus far continued to scale at the same rate since 90 nm. Comparing labels between companies is kind of silly. Specific dimensions, like minimum metal pitch, minimum contacted gate pitch and other such elements might give you some idea of relative density, but you also have to take into account what kind of design you are making and what sort of patterns are supported by the process, none of which is completely public. So the whole density pissing contest is rather meaningless. It's likely the first time we'll get to see a genuine apples to apples comparison will be when SoFIA comes out with Silvermont on 28 nm HPM. That should give us some idea of relative density for the same type of product.

 

[Khato]

Very interesting slides. TSMC expects a massive frequency increase from FINFets, and a small area shrink from 20 to 16ff.

Though keep in mind that their claimed improvements of 38% speed at same total power or 54% power saving at same speed compared to their 28nm HPM process are pretty much exactly the same as Intel's 22nm announcement. On page 22 of http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf Intel states a 37% performance increase at low voltage or >50% power reduction at constant performance. (While I know that TSMC doesn't state the low voltage stipulation on their speed increase it's more or less implied.)

That said, the one little tidbit we have thus far for TSMC's '16nm' process does imply that it will be a bit better than Intel's 22nm. Which isn't too surprising given that TSMC's 28HPM process, which only went into production last year with the Snapdragon 800 being the first product using it, is understandably a bit better than Intel's 32nm process that's been out since the start of 2010. Anyway, the abstract for TSMC's IEDM 2013 presentation - http://ieeexplore.ieee.org/xpl/logi...re.ieee.org/xpls/abs_all.jsp?arnumber=6724591 - states a 0.07um^2 SRAM cell size and 520/525 uA/um Idsat at 0.75V and 30 pA/um Ioff for their '16nm' process. This compared to Intel's 22nm SoC process - http://www.chipworks.com/en/technic...tel-details-22nm-trigate-soc-process-at-iedm/ - with something like a 0.092um^2 SRAM cell size and 410/370 uA/um Idsat at 0.75V and 30 pA/um Ioff.

 

[witeken]

That's pretty meaningless. There is nothing in the 22 nm node that's 22 nm. The node labels from a given company once used to indicate that the relative amount of scaling between the products. This has continued to hold true, especially if you look at the SRAM cell. Everyone's SRAM cell has thus far continued to scale at the same rate since 90 nm. Comparing labels between companies is kind of silly. Specific dimensions, like minimum metal pitch, minimum contacted gate pitch and other such elements might give you some idea of relative density, but you also have to take into account what kind of design you are making and what sort of patterns are supported by the process, none of which is completely public. So the whole density pissing contest is rather meaningless. It's likely the first time we'll get to see a genuine apples to apples comparison will be when SoFIA comes out with Silvermont on 28 nm HPM. That should give us some idea of relative density for the same type of product.

As far as I know, node naming was accurate until something called the MHz race came in.

You can find some very informative literature about Moore's law on the internet:

The Status of Moore's Law: It's Complicated

 

[witeken]

How do we actually know that those Broadwell SoCs have a GT3 IGP?

 

[Khato]

129mm²?

*The difference between (quadcore) GT2 and GT3 is 264mm² - 177mm² = 87mm².
*Dualcore ULT GT3 is 181mm².
That means dualcore GT2 is 181mm² - 87mm² = 94mm².
-> Broadwell is 63.4% of dualcore 94mm² GT2 Haswell = 59.60mm².

=> Dualcore GT3 Broadwell is 181mm² / 59.60mm² = 3x smaller than dualcore GT3 Haswell (without taking into account the extra transistors Broadwell probably has)

Is there something wrong with my calculation?

Your base assumption that the only difference in the die size between 4C GT2 and 4C GT3 is due to the graphics is incorrect. It's the same as stating that the difference between 4C GT3 and 2C GT3 is 264mm^2 - 181mm^2 = 83mm^2, therefore each Haswell core must add 41.5mm^2 to the design. Which is quite easy to invalidate No, if you check the released 4C GT2 die shot you end up with GT2 graphics using something around 50mm^2 I believe? Which should roughly be the same as the delta between GT2 and GT3 given that it's a simple duplication.

How do we actually know that those Broadwell SoCs have a GT3 IGP?

The ones in that picture are definitely 2C GT2.

 

[witeken]

Your base assumption that the only difference in the die size between 4C GT2 and 4C GT3 is due to the graphics is incorrect. It's the same as stating that the difference between 4C GT3 and 2C GT3 is 264mm^2 - 181mm^2 = 83mm^2, therefore each Haswell core must add 41.5mm^2 to the design. Which is quite easy to invalidate No, if you check the released 4C GT2 die shot you end up with GT2 graphics using something around 50mm^2 I believe? Which should roughly be the same as the delta between GT2 and GT3 given that it's a simple duplication.

As far as I know, my assumptions are correct, but I'd be happy to hear if they aren't so they could be made more accurate.

You say it's the same as comparing 4 core dies to 2 core dies. I don't agree. Dualcores are low-end, so they have less features on purpose, while a GT3 version most likely is the GT2 version with the GT3 IGP. A simple Google search result gives me a comparison of i7 4770S and i3 4330. The i3 has 50% of the cache of the i7: http://versus.com/en/intel-core-i3-4330-vs-intel-core-i7-4770s.

Or you can look at Wikipedia: http://en.wikipedia.org/wiki/Haswell_(microarchitecture))

There is a difference between a i7 4770K and R, the R has 2MB less L3 cache. But I don't see such things with the mobile processors: all Celerons and Pentiums have 2MB L3 cache, all i3s and i5s have 3MB L3 cache and all ULV i7s have 4MB of last level cache. I'm not sure if there are other things that could make meaningful differences.

That means the GT2 ULV Haswell should be 94mm². So unless the Broadwell CPUs are low-end, with less cache, or the IGP isn't a GT3, I don't think my calculations are wrong.


Also, your comment on GT2 die size seems to be wrong, I quote Anand: look below

Breaking things down to the GPU portion of Haswell, based in turn on these measurements I came up with an 87mm^2 adder for the extra hardware in Haswell GT3 vs. GT2. Doubling that 87mm^2 we get a rough idea of how big the full 40 EU Haswell GPU might be: 174mm^2.

The ones in that picture are definitely 2C GT2.

I'd like to quote the all knowing Homeles (who by the way started this whole discussion):

GT3 dual core Broadwell is 80mm2. It's not that hard to imagine that two extra cores will still be well under 150mm2.

My question is how does he know that the dualcore Broadwell CPU from the picture has a GT3 IGP? If that's wrong, I guess my whole estimate of the density advantage of 14nm is wrong.

-------

While I was writing this reply, I was realizing something that confuses me a lot: like I already said some times, according to Anand 20 EUs cost 87mm² of die space. Double that and Anand comes up with 174mm² for the GT3 parts of the die. Okay, but now I just looked at GT3 i3 die size and realized: how is it possible that 2 cores, cache and all the other stuff besides the IGP have only 7mm² of space left?!

My calculation is obviously wrong. I'll try to figure out what's wrong and come up with something better. Some help is appreciated.

 

[Exophase]

While I was writing this reply, I was realizing something that confuses me a lot: like I already said some times, according to Anand 20 EUs cost 87mm² of die space. Double that and Anand comes up with 174mm² for the GT3 parts of the die. Okay, but now I just looked at GT3 i3 die size and realized: how is it possible that 2 cores, cache and all the other stuff besides the IGP have only 7mm² of space left?!

My calculation is obviously wrong. I'll try to figure out what's wrong and come up with something better. Some help is appreciated.

Some good die shots might be helpful in trying to ascertain this, but the simplest explanation is that the quad core GT3 part needs space for more than just the difference from GT2 to GT3. One thing overlooked is the support for the off-chip eDRAM. We know it's used as a cache, meaning that there could be a tags array kept as SRAM on the chip. The requirements for tag RAM of a 128MB cache could be as vast as dozens of MB, depending on the line size.

 

[Homeles]

This image from Apple's 2013 rMBP announcement uses a shot of GT3e. Terrible quality, but maybe I can find something better by using that as a starting point.

 

[AtenRa]

If i remember correctly, GT3 iGPU size in the Dual core die is 100-110mm2 out of the 181mm2 of the entire die.

Intel Reveals New Haswell Details at ISSCC 2014

ps: those pics above are not in scale.

 

[Khato]

As far as I know, my assumptions are correct, but I'd be happy to hear if they aren't so they could be made more accurate.

You say it's the same as comparing 4 core dies to 2 core dies. I don't agree. Dualcores are low-end, so they have less features on purpose, while a GT3 version most likely is the GT2 version with the GT3 IGP. A simple Google search result gives me a comparison of i7 4770S and i3 4330. The i3 has 50% of the cache of the i7: http://versus.com/en/intel-core-i3-4330-vs-intel-core-i7-4770s.

Regarding the cache sizes, it's actually pretty simple. Each Haswell core has 2MB of L3 cache associated with it. Hence the maximum L3 cache for quad core parts in 8MB while for dual core parts it's 4MB. (Note that I'm not a hundred percent certain if the 4C GT3 parts also have the full 2MB of L3 cache per core or if Intel chopped it down to 1.5MB.) Anyway, lower end parts have portions of the L3 cache disabled, both to differentiate SKUs and potentially to make use of a chip with a defect in the L3. (I believe they only have 4 layouts that make up all of their desktop/mobile SKUs, 2C GT2, 2C GT3, 4C GT2, and 4C GT3.)

While I was writing this reply, I was realizing something that confuses me a lot: like I already said some times, according to Anand 20 EUs cost 87mm² of die space. Double that and Anand comes up with 174mm² for the GT3 parts of the die. Okay, but now I just looked at GT3 i3 die size and realized: how is it possible that 2 cores, cache and all the other stuff besides the IGP have only 7mm² of space left?!

My calculation is obviously wrong. I'll try to figure out what's wrong and come up with something better. Some help is appreciated.

It's unfortunate that Anand never went back to correct that article since it was rather obvious from the start that his 87mm^2 for 20 EUs on Haswell was incorrect. My guess as to the cause of the 4C GT3 having a markedly larger die size than would be expected for the expected delta compared to either 2C GT3 or 4C GT2 is that it's using a completely different layout that likely isn't as optimal. Which is to say that going the 'tall and skinny' route that all the components were designed for wouldn't work for a 4C GT3 (most likely the length would exceed the maximum), and hence they switched to a side-by-side configuration which is why it's the only Haswell die that looks roughly square instead of rectangular. (They do the same thing on the high core count Xeon/extreme processors.) Only problem being that the height of the 4 cores + SA doesn't match up with GT3/there's not really a good way to take the same building blocks for the rectangle and make a perfect square. Which means they either a slight hit on die size for a comparatively low volume product or do as much layout work for that one SKU as they did for the other three.

If i remember correctly, GT3 iGPU size in the Dual core die is 100-110mm2 out of the 181mm2 of the entire die.

Intel Reveals New Haswell Details at ISSCC 2014

ps: those pics above are not in scale.

Nice find. That Chip size range pretty much leaves no question as to what the 2C GT2 and 4C GT3 die sizes are And the transistor counts also imply what I'm guessing above - 4C GT3 is double the die size of 2C GT2 but only has 1.77x the transistors.

 

[witeken]

I will calculate the density improvement of 14nm (I will refer a few times to the image above this post)

* Broadwell's die is 64.5% of Haswell's (the dies of Anand's picture).
* GT2 is 31.9% of QC i7 die size = 56.46mm².

(If you look at the picture above, you can clearly see that the other 20 EUs are mirrored from the 20 EUs of GT2. I wonder however why I can only see 32 EUs at the die above: the 'Quad-Core' has 4 times 2 EUs and 2 times a single EU, while the 'Dual-Core' has 8 times 2 EUs without the suspected 4 times 1 EU.)

Above the EU in 'Graphics', there is a small portion that I won't count in my calculations (when I took the GT2 percentage of i7 4770's die, that protion was included, but when I subtract 56.46mm² from 181mm², I would have subtracted a non-existent portion of a GT3 die (that only exists in the GT2 portion of the die), but that portion isn't that big that I don't bother).

* If you take the 181mm² dualcore ULT GT3 die, and subtract 56.46mm² from it, and take 64.5% of that number, you get 80.33mm² indeed. Just like someone calculated.


But this isn't where the calculation ends!!!

We need to take into account the extra EUs of Broadwell to be able to calculate the density improvement of Broadwell. Broadwell will have 20% more EUs. The EUs aren't everything of the IGP, but let's assume that the architectural improvements + extra EUs make the whole IGP 30% larger.

* (2*56.46mm² * 1.3) - 2*56.46mm² = 2*16.94mm² = 33.88mm² more area. GT2 is 56.46mm², but we need to know how much extra area a Broadwell GT3 would have, so I multiplied it by 2.

* 181mm² + 34mm² = 215mm² for a 22nm GT3 Broadwell IGP (inside a 181mm² dualcore ULT GT2 Haswell processor, with the IGP replaced by a hypothetical Broadwell IGP).

-We know what the size of a dualcore Haswell with 24 Broadwell EUs is: 214.88mm²
-We know what the size of a dualcore Broadwell GT3 is: 80.33mm²

Divide those guys, and the result is: 2.675

Here you have it: 14nm will give about a 2.675 times density improvement over 22nm.

Fun facts: If you look at the pure numbers, 22nm -> 14nm would give (22nm / 14nm)² = 2.47x density improvement. Also, earlier today I was trying to calculate the improvement via Intel's infamous density slide (vs. TSMC) and I got about 2,7x improvement if I did the assumption that 32->22 would give 2x density improvement and extrapolated the 32->22nm line to 14nm and compared the result of the extrapolated line vs. Intel's 14nm forecast.

Edit: I can't believe I spent quite some time figuring out dualcore GT2 Haswell die size while Intel had already released it while I was typing... (I saw the image above this post, but didn't know it was from a new pipeline story).
Edit 2: Why does it say that ULT Haswell is 180mm²? Please don't say my calculation are wrong ;(

@Khato: Thanks for your useful insights.

 

[witeken]

(I believe they only have 4 layouts that make up all of their desktop/mobile SKUs, 2C GT2, 2C GT3, 4C GT2, and 4C GT3.)

Not sure. I saw following presentation of Haswell yesterday, it says that there are 11 dies: http://www.youtube.com/watch?v=FWXTBIY3dzA.

"Haswell to begin with it is not just one chip or product. It's a family of products. In the lower right corner you can see some of the different die that we enable."

~36:30

 

[ame132]

some old info on haswell configurations
http://wccftech.com/haswell-die-configurations-intel-ivy-bridge-revealed/

 

[Khato]

Huh, quite interesting. Somehow I missed that they actually did a separate layout for a GT1 with Haswell still, had thought that was just a fuse disable. Also quite interesting to see that there's a separate 'ULT version' for both the mobile dual cores. I guess it does make sense since such allows them to tweak it for lower power, but still surprising.

 

[jpiniero]

The ULT model must have some additional logic to deal with the communication with the on package PCH.

 

[Homeles]

The ULT model must have some additional logic to deal with the communication with the on package PCH.

That would also explain why it's not enabled on mainstream notebook processors, although it's not like Intel doesn't arbitrarily disable features.

 

[Phynaz]

The ULT model must have some additional logic to deal with the communication with the on package PCH.

The Haswell ULT variants use Intel's on-package IO to connect the CPU/GPU island to an on-package PCH - the eDRAM interface.