Interesting dispute brewing between Intel/TSMC

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witeken

Diamond Member
Dec 25, 2013
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1. Five of the eight points are marked as "Forecast", even choosing words like "actual" or "data" is inappropriate for something like this. Not to mention we don't see a scale, not even a description for the Y axis, other than log scale. There is the old conundrum of whether logarithms should have units or not. I seem to remember I was taught to normalize units (off) before applying the logarithm function, so we can't have units as description, I guess. Well I had to infer that the Y-Axis denotes "area" from the slide title. But which area still remains vague, is it area to place a certain IC or is it just trivial Y = X² area of a square, that shrinks as you shorten the sides. I lean toward the latter.

2. What does the chart set out to show for the immediate future, with it's completely convoluted way to present data, It shows that 14nm is more dense than 16nm. Wow, guess what node also would be more dense than 16nm?
A. 15nm
B. 14nm
D. 13nm
E. 12nm
F. All of the above
Intel used that graph to show that they're committed to continue Moore's law, and even at a faster pace than today, while 'competitors' (TSMC) are stagnating (upper left graph):


Your graph isn't based on the number (e.g. 14nm < 16nm) but on real forecasts from Intel and TSMC.


3.Typically every node shrink is chosen such, that it basically halves the area. Twice as many transistors for the same area hence Moore's law and all that. This would read as 50% ahead in the chart presumably(?).
Intel's chart shows TSMC's [20] and [16] nodes at about the same hight. Why would TSMC go from 20 to 16ff if there is no area / no cheaper production to recoup the investments to be gained?
Because they want to catch up with Intel (or at least make it look like that), so they do 16nm 1 year after 20nm. But in fact 16nm is just 20nm, but the planar transistors are replaced with FinFETs.

Also according to this graph the upcoming 14 nm process will only be 35% ahead of TSMCs 20 nm. Which should be good news for TSMC, since they both should arrive at the same time.
Yes, but as you can see from Intel's graph, 16nm won't bring a lot of improvements, so Intel will have 10nm for almost 2 years before TSMC has another transistor shrink with 10nm. By then, Intel will have 7nm. Intel's point is that their equivalent node to TSMC's (e.g. 16nm and 14nm, 10nm and 10nm) will have a smaller area and also Intel will be 1 node ahead of TSMC, so Intel should have a huge advantage (equivalent to 2 nodes) on TSMC.
 

Third_Eye

Member
Jan 25, 2013
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That same author has written many critical pieces about Intel, too ;-)

For example...

http://seekingalpha.com/article/1935731-intels-merrifield-looks-dead-on-arrival



And, look, he's even positive on TSMC!

http://seekingalpha.com/article/1722462-taiwan-semiconductor-looks-undervalued-ahead-of-key-drivers

Gee, guess it's possible to be objective *and* own stocks! What a concept!
LOL! Look at Ashraf Essa's articles in 2013.
He did a 180 on Intel only from Dec 2013. Till then he was badmouthing TSMC.
I had commented on some of his articles as well as others who use his analysis to derive conclusions.
His analysis was sometimes as simple as stating
a) Intel is 22nm FinFET today
b) TSMC is at 28nm Bulk HKMG and will not move to FinFETS till 16nm.
c) By the time TSMC goes on 20nm Bulk HKMG, Intel will strengthen itself by producing chips at 14nm FinFET having an unassailable lead in process, node as well as complexity.
d) So Intel wins. Blah!Blah!Blah!
stating that it is not as simple as that.
 

Khato

Golden Member
Jul 15, 2001
1,225
280
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18nm is the max precision of ASMLs most advanced available tools
and that is with double or even triple patterning.

ASML’s TWINSCAN NXE platform is the industry’s first production platform for extreme ultraviolet lithography (EUVL). The NXE:3300B is the successor to the NXE:3100, offering 22 nm resolution with conventional illumination and 18 nm with off-axis illumination as well as improved overlay and higher productivity.

http://www.asml.com/asml/show.do?lang=EN&ctx=46772&dfp_product_id=842

Again? http://forums.anandtech.com/showthread.php?p=35623288&highlight=nxe#post35623288

Since I guess you forgot, Intel has been quite clear that they are not using EUV for 14nm, and most likely not for 10nm either. Yet for some reason you continue to claim that they're going to make use of an EUV tool when everyone who understands the industry knows otherwise? ASML is getting closer to having the wph near the necessary levels, but there are still multiple other issues to work the kinks out of before it can be used in high volume production.

Further, even if they were using the above EUV system the resolution that you're quoting is merely the guideline for single patterning. It can be tweaked lower, as evidenced by everyone going below ASML's stated 38nm resolution for single patterning on their immersion ArF systems.
 
Mar 10, 2006
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LOL! Look at Ashraf Essa's articles in 2013.
He did a 180 on Intel only from Dec 2013. Till then he was badmouthing TSMC.
I had commented on some of his articles as well as others who use his analysis to derive conclusions.
His analysis was sometimes as simple as stating
a) Intel is 22nm FinFET today
b) TSMC is at 28nm Bulk HKMG and will not move to FinFETS till 16nm.
c) By the time TSMC goes on 20nm Bulk HKMG, Intel will strengthen itself by producing chips at 14nm FinFET having an unassailable lead in process, node as well as complexity.
d) So Intel wins. Blah!Blah!Blah!
stating that it is not as simple as that.

I don't ever think he stated it was as simple as that; his mistake was probably believing that Intel's SoC design teams would be able to effectively leverage this process lead at the 22nm generation. And I've read every single one of his articles...
 

Khato

Golden Member
Jul 15, 2001
1,225
280
136
3.Typically every node shrink is chosen such, that it basically halves the area. Twice as many transistors for the same area hence Moore's law and all that. This would read as 50% ahead in the chart presumably(?).
Intel's chart shows TSMC's [20] and [16] nodes at about the same hight. Why would TSMC go from 20 to 16ff if there is no area / no cheaper production to recoup the investments to be gained?

They're doing so in order to 'catch up' to Intel in implementing FinFET transistors sooner than they would if they were doing a full node shrink. Even in this latest presentation they're only claiming a 15% density improvement going from 20nm to '16nm', a far cry from the ~36% improvement that the node labels imply. (Not that I'm going to fault them for such seeing as how it's standard practice.) And back before they were trying to market against Intel they were only expecting a 1.1x density increase - page 19 of http://www.eda.org/edps/EDP2013/Papers/4-4 FINAL for Tom Quan.pdf

Also according to this graph the upcoming 14 nm process will only be 35% ahead of TSMCs 20 nm. Which should be good news for TSMC, since they both should arrive at the same time.

Depends. I suspect that Intel simply made the 20nm to '16nm' density line for TSMC flat to illustrate the effect while the 35% density advantage is based on TSMC's stated 2x density increase going from 28nm to '16nm'.
 

AtenRa

Lifer
Feb 2, 2009
14,003
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Intel used that graph to show that they're committed to continue Moore's law, and even at a faster pace than today, while 'competitors' (TSMC) are stagnating (upper left graph):

If things were that simple, Core i7 4770K would be priced at $50. That graph(upper left) only tells half the story, the other half is that Intel and every Fab in the world needs approximately double the spending's to research and manufacture ready the next process. That makes each IC or Processor if you like, cost the same or more than before.

And that happens because the next Processor never have the same transistor count as the one that replaces. The transistor count is always on the rise (to gain performance) and that affects the die size. The IC or CPU would be cheaper only if we would keep the same transistor count of the last gen processor with the new process in order to shrink the die 70%. That way we would spend 2x the amount to have the new process but we would produce 2x or more dies per wafer.

Not only that, but each new process may as well be more manufactured expensive than the one before it. For example, Intels 22nm FinFet is more expensive than 32nm planar. 22nm FinFet has more stages than 32nm and that also affect the cost per Wafer and each die. Not to mention early lower yields than older process.
 

Abwx

Lifer
Apr 2, 2011
11,167
3,862
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Again? http://forums.anandtech.com/showthread.php?p=35623288&highlight=nxe#post35623288

Since I guess you forgot, Intel has been quite clear that they are not using EUV for 14nm, and most likely not for 10nm either. Yet for some reason you continue to claim that they're going to make use of an EUV tool when everyone who understands the industry knows otherwise? ASML is getting closer to having the wph near the necessary levels, but there are still multiple other issues to work the kinks out of before it can be used in high volume production.

Further, even if they were using the above EUV system the resolution that you're quoting is merely the guideline for single patterning. It can be tweaked lower, as evidenced by everyone going below ASML's stated 38nm resolution for single patterning on their immersion ArF systems.

So tell us what they are using if it s not ASMLs most recent gear,
actualy you dont know nothing and are just doing random claims.

Besides , you dont read accurately , as demonstrated by the bolded
part in your post..

ASML’s TWINSCAN NXE platform is the industry’s first production platform for extreme ultraviolet lithography (EUVL). The NXE:3300B is the successor to the NXE:3100, offering 22 nm resolution with conventional illumination and 18 nm with off-axis illumination as well as improved overlay and higher productivity.

Do you ignore that Intel is an ASML share holder..??.
 

GreenChile

Member
Sep 4, 2007
190
0
0
1. Five of the eight points are marked as "Forecast", even choosing words like "actual" or "data" is inappropriate for something like this. Not to mention we don't see a scale, not even a description for the Y axis, other than log scale. There is the old conundrum of whether logarithms should have units or not. I seem to remember I was taught to normalize units (off) before applying the logarithm function, so we can't have units as description, I guess. Well I had to infer that the Y-Axis denotes "area" from the slide title. But which area still remains vague, is it area to place a certain IC or is it just trivial Y = X² area of a square, that shrinks as you shorten the sides. I lean toward the latter.
The chart's forecasting is based on information that is publicly known and reasonable assumptions about projected density scaling.

2. What does the chart set out to show for the immediate future, with it's completely convoluted way to present data, It shows that 14nm is more dense than 16nm. Wow, guess what node also would be more dense than 16nm?
A. 15nm
B. 14nm
D. 13nm
E. 12nm
F. All of the above

3.Typically every node shrink is chosen such, that it basically halves the area. Twice as many transistors for the same area hence Moore's law and all that. This would read as 50% ahead in the chart presumably(?).
Intel's chart shows TSMC's [20] and [16] nodes at about the same hight. Why would TSMC go from 20 to 16ff if there is no area / no cheaper production to recoup the investments to be gained?

Also according to this graph the upcoming 14 nm process will only be 35% ahead of TSMCs 20 nm. Which should be good news for TSMC, since they both should arrive at the same time.
TSMC has publicly stated that they will not scale down the metal pitch going from 20nm to 16nm. This has been stated repeatedly in this thread and is the reason the why the graph shows no scaling for TSMC going from 20nm to 16nm. TSMC is simply replacing planar transistors with finfet transistors. Calling this a node shrink is would be inaccurate.
 

tarlinian

Member
Dec 28, 2013
32
0
41
So tell us what they are using if it s not ASMLs most recent gear,
actualy you dont know nothing and are just doing random claims.

Besides , you dont read accurately , as demonstrated by the bolded
part in your post..



Do you ignore that Intel is an ASML share holder..??.

No one is using EUV for production for another 5+ years. It's clearly stated in public by everyone. If you're trying to claim otherwise, you're just making a fool of yourself.

And linewidths are not limited by lithography. You can add additional spacer dep and etch steps to halve pitch. Lithography limits edge placement error in the era of multi-patterning, not absolute feature size. In addition, EUV achieves 18 nm half-pitch with single patterning, not double patterning.
 

Khato

Golden Member
Jul 15, 2001
1,225
280
136
So tell us what they are using if it s not ASMLs most recent gear,
actualy you dont know nothing and are just doing random claims.

Can't do anything more than speculate as to which tools exactly they're using seeing as how it's not public information. But if they're using ASML equipment then it'd likely be something in either the NXT or XT line.

Besides , you dont read accurately , as demonstrated by the boldedpart in your post..

Do you ignore that Intel is an ASML share holder..??.

No, I read just fine. Here's some reading for you:

Mark Bohr Interview : http://www.behardware.com/articles/877-1/idf-interview-with-intel-s-mark-bohr.html
We were talking previously about EUV and the fact that it's been coming soon for a very long time, in the meantime 193nm lithography seems incredibly resilient. Did it surprise you how far you've been able to push 193nm litho ?

MB : If you had asked me ten years ago, "do I need EUV by 14nm", I would have said yes! So, even I have been surprised at the type of innovations our research has provided to extend immersion. So that's the good news.

A lot of these gains came from immersion in your perspective?

MB : Most of the gains from immersion itself were realized at the 32nm generation and then going forward from that we started to introduce double patterning and even triple patterning techniques. So that, combined with some other mask making improvements have enabled immersion to extend down to 22, and 14, and I know we have an immersion solution for the 10nm generation. Now, can immersion be extended to 7 ? We don't know yet. We're exploring that option; we are also pushing to advance EUV as quickly as we can.

Justin Rattner Interview : http://www.theregister.co.uk/2013/05/29/euv_lithography_still_out_there/
The problem is not a purely academic one, according to Rattner. &#8220;I think it's the case we&#8217;re going to reach a point before the end of the decade where in the absence of a reliable EUV lithography technology that we&#8217;re going to have trouble dealing in the next critical dimension.

&#8220;It&#8217;s a necessary technology. We&#8217;re OK at 22(nm), we&#8217;re OK at 14, we&#8217;ll probably get to 10. Then maybe it's going to get tougher,&#8221; he said.

Another Justin Rattner Interview : http://www.technologyreview.com/news/516311/intels-justin-rattner-on-new-laser-chip-business/
Is it getting more challenging to keep Moore&#8217;s Law going?

Things are very small, and the physics is no doubt challenging. We can see ahead two, maybe three, generations and we feel pretty good about that, but beyond that it starts to get a little fuzzy. Lithography is a huge one. Everybody expected that we&#8217;d make this transition to EUV [extreme ultraviolet], and it hasn&#8217;t happened. EUV lithography is just inherently more expensive, so that&#8217;s one concern on the horizon.

Random recent article on EUV : http://www.eetimes.com/document.asp?doc_id=1319748
The development of the latest MOPA light source for EUV put the weakest component in the long-delayed lithography system on a more steady footing, they said. Researchers now expect to demo an 80W light source in a working system by the end of the year, a 125W version next year and a 250W one capable of driving commercial throughput of 125 wafers/hour by the end of 2015.

At that cadence, chip makers still need to rely on prior generation immersion lithography for their initial offering of 10nm technology. However, they could be able to insert a pilot line of EUV at the same time, cutting over at least a few critical steps soon afterwards.

Oh, and how about the most obvious indication that they're not being used for Intel's 14nm volume production straight from ASML? : http://www.asml.com/asml/show.do?ctx=41905&rid=41906
How many EUV systems has ASML sold?
Apart from the two prototype machines (see above), ASML had orders for six NXE:3100 systems, all of which have been shipped. ASML has received 11 orders for the following model, NXE:3300B. The first of those systems were shipped at the end of 2013, with shipments continuing in 2014.

Page updated on 2014-1-23 0:00

And sorry for the quote-fest, but I don't take kindly to being told that I "don't know nothing and are just doing random claims" when it's quite obvious that it's the other way around.
 

Phynaz

Lifer
Mar 13, 2006
10,140
819
126
So tell us what they are using if it s not ASMLs most recent gear,
actualy you dont know nothing and are just doing random claims.

Besides , you dont read accurately , as demonstrated by the bolded
part in your post..



Do you ignore that Intel is an ASML share holder..??.

Please tell us the following for Intel's EUV process.

What material are they using for the lens? (Glass is opaque to EUV)
What fluid are they using for immersion? (Water based fluids are opaque to EUV and boil away in vacuum)
What chemical are they using for photo etch? (Current etch chemicals aren't sensitive to EUV)
When did they build a vacuum assembly line? (Air is opaque to EUV)
What have they done to overcome the source power problem?
How many WPH are they running?

http://www.eetimes.com/author.asp?section_id=36&doc_id=1318891
Intel -- which last year acquired a 15 percent stake in ASML and ponied up additional funds specifically for the development of EUV in a deal worth a total of $4.1 billion -- has been hoping to deploy EUV lithography at the 10 nm node in the second half of 2015. Intel also said it would be prepared to extend optical immersion lithography to that node in the event that EUV is not ready.

You're getting in over your head, and we aren't the ones making the random claims.
 
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tarlinian

Member
Dec 28, 2013
32
0
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What material are they using for the lens? (Glass is opaque to EUV)
What fluid are they using for immersion? (Water based fluids are opaque to EUV and boil away in vacuum)
What chemical are they using for photo etch? (Current etch chemicals aren't sensitive to EUV)
When did they build a vacuum assembly line? (Air is opaque to EUV)
What have they done to overcome the source power problem?
How many WPH are they running?

EUV doesn't use lenses, it's entirely reflective, has no need for immersion because of the wavelength and existing tools run in a vacuum. Plenty of EUV resists exist, but require a relatively high dose. That's why source power is a problem and throughput is way too low for production. The low source power is the main problem with EUV. The other problem is mask defects. The blanks have too many defects and there's no good way to protect masks during processing right now. There is work being done on a pellicle to protect EUV masks but it will result in a need for even higher source power to account for the absorption of the pellicle.
 

witeken

Diamond Member
Dec 25, 2013
3,899
193
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If things were that simple, Core i7 4770K would be priced at $50. That graph(upper left) only tells half the story, the other half is that Intel and every Fab in the world needs approximately double the spending's to research and manufacture ready the next process. That makes each IC or Processor if you like, cost the same or more than before.
Do you have a source for that? Even if it were true, the 2x lower costs would eventually pay back the R&D, so Moore's law could continue anyway. Costs are indeed rising and they want to be safe indeed, so they're not giving i7s away for $50.

But everything you say in this post can also be applied to other companies like TSMC or Samsung, and you should be least worried about Intel.

And that happens because the next Processor never have the same transistor count as the one that replaces. The transistor count is always on the rise (to gain performance) and that affects the die size. The IC or CPU would be cheaper only if we would keep the same transistor count of the last gen processor with the new process in order to shrink the die 70%. That way we would spend 2x the amount to have the new process but we would produce 2x or more dies per wafer.
If you look at Intel's CPU die sizes, they have shrunk over the past years:

Broadwell will go well below 150mm² for the first time since 2006, certainly if Intel's famous density claims are true (it look like almost 2 full nodes, so maybe up to 3x higher density?).

So it looks like Intel is trying to get higher margins on their CPUs by not doubling transistor count every die shrink. And even then, Nvidia's 550mm² GK110 has a lower consumer cost/mm² on a worse TSMC process node while they're a fabless company (= lower margins), so I don't think Intel has any problems.
 

Abwx

Lifer
Apr 2, 2011
11,167
3,862
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Seems that my post attracted a lot of rebuke that could of course
be true but ironicaly if EUV is not used then the 14/16nm claim is even
more erroneous , likely that size although reduced substancialy is nowhere
close to a 2 ratio and that it s the layout that benefit more from this node
shrink allowing to pack more transistors even if their actual size is not that
much reduced.
 

witeken

Diamond Member
Dec 25, 2013
3,899
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No one is using EUV for production for another 5+ years. It's clearly stated in public by everyone. If you're trying to claim otherwise, you're just making a fool of yourself.
Source? 2014 + 5 years is 2019, which would mean that Intel would be using EUV later than 450mm wafers. I'm also not sure how they're going to make 5nm transistors with current technologies. Quadruple patterning?

But I just searched on Google and stumbled across this insanely long Wikipedia page, which gives some useful facts.

Extreme Ultraviolet Lithography

It states that the quoted NXE:3300B from this thread is succeeded by the NXE:3300C, which improves resolution from 22nm to "16 nm if <7 nm resist diffusion length" with a throuput goal from 125WPH to 150WPH (which I heard they will reach in 2014).

Apparently, EUV will be first used at 7nm, which seems a bit late to me (but still earlier than your 5+ years).
At the 2013 EUVL Workshop, Intel announced that EUV would still be under development in 2015, and hence would be targeted for 2017 7 nm HVM. Consequently, 10 nm would be carried out with ArF immersion multiple patterning.[189] TSMC[190] and GlobalFoundries[191] have made similar statements.
 

tarlinian

Member
Dec 28, 2013
32
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Source? 2014 + 5 years is 2019, which would mean that Intel would be using EUV later than 450mm wafers. I'm also not sure how they're going to make 5nm transistors with current technologies. Quadruple patterning?


I guess I mean that we won't see it in production chips for 5 years. Even then everything relating to EUV has taken at least twice as long as publicly stated roadmaps. Roadmaps from a few years ago indicated that we would be a production level (100+ W) source power by now. There's been improvement, but not that much and I expect to rate of improvement to not really speed up. Realistically, someone has to come up with a better way of generating the light than with LPP. There are also some presentations from Yan Bordovsky floating around that say you really need to reach 1000 W to use EUV for certain layers (like contact holes), where it's really useful.
Even now, EUV will most likely be used by Intel (and maybe everyone else if it takes long enough) for cutting gratings in order to reduce the number of cut masks you would need when compared to 193i. Pitch will probably still be defined by spacer based patterning because it's a nice mature technique which doesn't require a $100 M tool. No one's going to spend that kind of money when they can avoid it. Quadruple patterning is completely viable, it's used in NAND right now (for simpler structures admittedly, but it's not impossible).
 

AtenRa

Lifer
Feb 2, 2009
14,003
3,361
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Do you have a source for that? Even if it were true, the 2x lower costs would eventually pay back the R&D, so Moore's law could continue anyway. Costs are indeed rising and they want to be safe indeed, so they're not giving i7s away for $50. (1)

But everything you say in this post can also be applied to other companies like TSMC or Samsung, and you should be least worried about Intel. (2)


If you look at Intel's CPU die sizes, they have shrunk over the past years:

Broadwell will go well below 150mm² for the first time since 2006, certainly if Intel's famous density claims are true (it look like almost 2 full nodes, so maybe up to 3x higher density?). (3)

So it looks like Intel is trying to get higher margins on their CPUs by not doubling transistor count every die shrink. And even then, Nvidia's 550mm² GK110 has a lower consumer cost/mm² on a worse TSMC process node while they're a fabless company (= lower margins), so I don't think Intel has any problems.(4)

(1) There was a PDF outlining the cost rise of new Processes and designing cost for a new Chip but i cant find it now. But 22nm dies doesnt cost 2x less than 32nm. For example, 22nm 4770K die is not 2x cheaper than 32nm 2600K.
Even without taking the R&D cost of the process in to consideration, 4770K is 170mm2 and 2600K is 240mm2. With the same 80% yields for both of them, you get 193 dies for the 2600K and 275 dies for the 4770 per wafer.
Now because 22nm is more expensive to manufacture the wafers due to more stages in the process, the wafer cost will be higher than 32nm. lets assume it will be 20% more expensive, so if 32nm wafer costs $4000 then 22nm will cost $4800.
Now lets see how much each die cost,

Core i7 2600k with 80% yield will get 193 dies per wafer, each die will cost 4000/193 = $20,72

Core i7 4770k with 80% yield will get 275 dies per wafer, each die will cost 4800/275 = $17,45

Core i7 4770K is only 15,78% cheaper than Core i7 2600K.

And that without taking the R&D cost in to consideration.

(2)
As i have said, that applies for every Fab in the world and not only Intel, i have just taken Intel products to showcase what is going on.

(3) Are you sure Broadwell Core i7 will be bellow 150mm2 ??? Because if Intel will increase the iGPU it will affect the die size as well.

(4) Im not saying Intel has a problem, im saying that Cost per Transistor is irrelevant for the consumer. CPUs at the same segment are not becoming cheaper per new process for the manufacturer or the consumer. A Core i7 in 2008 (Nehalem) cost the same as Core i7 today (Haswell) although transistor cost has fallen dramatically since then.
AMDs and NVIDIAs 28nm products price have risen significantly since 40nm, even though Cost per Transistor has fallen. That happen because die size hasn't shrank(GF110 is almost the same die size as GK110) from one process to the other, wafer cost risen from 40nm to 28nm and sales volume remained the same or fallen, both of AMD and NVIDIA raised the prices of their products.
Intel did the same, 2600K was released at $329 MSRP, Core i7 4770K is at $350 MSRP.
 

witeken

Diamond Member
Dec 25, 2013
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(3) Are you sure Broadwell Core i7 will be bellow 150mm2 ??? Because if Intel will increase the iGPU it will affect the die size as well.
I'm not sure, because Intel hasn't given a lot of (relevant) information about Broadwell. If Broadwell will get GT3 instead of GT2, it might be close, depending on how accurate Intel's forecasts are.
 

Homeles

Platinum Member
Dec 9, 2011
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(3) Are you sure Broadwell Core i7 will be bellow 150mm2 ??? Because if Intel will increase the iGPU it will affect the die size as well.
GT3 dual core Broadwell is 80mm2. It's not that hard to imagine that two extra cores will still be well under 150mm2.
 

witeken

Diamond Member
Dec 25, 2013
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Did Intel publish any Broadwell die size number? Do you have a link?

2C Haswell with GT3 is 181mm² if this is what you had in mind. Two cores add 80mm².
http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

This is everything we know: A Closer Look at Broadwell & its New Small Form Factor Package.

He ends the article with "I'm running between meetings now - but anyone want to use the photos here and our Haswell die area info to come up with an estimate for Broadwell SFF package size and Broadwell die size? " followed by estimates in the comments.

Edit: If 2C GT3 Haswell is 181mm², and Broadwell 2C GT3 is 80mm², that means at least a nice 2.26x die size reduction! Potentially even more (up to 3x), because Broadwell has probably more transistors.
 
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Nothingness

Platinum Member
Jul 3, 2013
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This is everything we know: A Closer Look at Broadwell & its New Small Form Factor Package.

He ends the article with "I'm running between meetings now - but anyone want to use the photos here and our Haswell die area info to come up with an estimate for Broadwell SFF package size and Broadwell die size? " followed by estimates in the comments.
Thanks for taking the time to give a proper answer

@Homeles: great, you've known this for months. Does that forbid people to ask?

Edit: If 2C GT3 Haswell is 181mm², and Broadwell 2C GT3 is 80mm², that means at least a nice 2.26x die size reduction! Potentially even more (up to 3x), because Broadwell has probably more transistors.
mikk gave two estimates: 126mm² for Haswell vs 80mm² for Broadwell, while Anand said that Haswell ULT should be 181mm². I'm confused :$ Is Anand including the second die that's in the package?

It's possible that the density increases more than expected because the 22nm process doesn't seem to have been designed for density. I wonder what increased density will mean, there generally is a hit in performance.
 
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Homeles

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Dec 9, 2011
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@Homeles: great, you've known this for months. Does that forbid people to ask?
Wasn't directed at anyone in specific. I'm just surprised that people don't know it.

But yeah, you have pointed out something interesting. mikk's Haswell estimate is off, resulting in an erroneous Broadwell estimate. If we assume he wasn't incorrect about Broadwell being 63.4% of the size of Haswell, that would put Broadwell ULT at 115mm2. That would put a quad core GT3 config at a tad over 150mm2.
 
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