Is Intels fabrication process advantage shrinking?

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Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
Actualy density is all TSMC can offer , their electrical parameters being vastly inferior to either intels or glofos
most refined processes.

You are comparing two nodes which were unavailable to any external customer, regardless the electrical parameters, for the vast majority of the time in which TSMC's 28nm has been commercially available and shipping in volumes.

Comparing Intel or GloFo to what TSMC offers is purely an academic argument if you were/are a fabless company for the past two years. Regardless what technical deficiencies you may assign to TSMC's 28nm, the bottom line is it was the only game in town for fabless companies for nearly 2 solid years.

Availability trumps inaccessible, unreliable, and inconsistent any day of the week when you are spending 2-3 yrs designing a product.

Currently prices being the main factor they have plenty
of cost restricted customers but if ever the competition
increase , and it is with intel targeting the lowly priced chips ,
any foundry that has superior process will highjack their
customer base , as it happened with qualcomm switching
to glofo to benefit from a more advanced process.

We have yet to determine what, if anything, is really afoot with Qualcomm.

But what we do know is you cannot transcend the time requirements involved in redesigning and laying out your chip (yet again) for a second foundry. There is no such thing as "hijacking" a customer at this late stage of the game.

If Qualcomm is producing chips at GloFo then Qualcomm made the decision to do so some 2 years ago (minimum) as that is the time required to port an existing vetted IC design from one foundry to another.

In the foundry business, the only time you have to intercept customers and steal them away from the competition is during the early stages of the node's development.

If GloFo wanted a customer for 2013 (like Qualcomm) then GloFo would have had to convince that customer to start designing their chips for GloFo's process flow no later than 2011.

If that is "hijacking" then it has to be the slowest darn robbery there ever has been.

You can forget the two years dev cycle for both 10nm
and 7nm , theses are no more trivial nodes , current tools
are to be replaced completely as they wont be extendable
past 14nm.

The development cycle for nodes has NOT been 2 years since roughly 1992.

Node development has historically been a 4 year effort, at least for the past 20 years.

Nodes are developed in parallel. A new node is formally* started in development every 2 yrs, with two nodes perpetually in the pipeline, staggered by two years so they come to production every two years.

At Intel, for example, 14nm has been in "development**" for ~3 yrs, 10nm has been in development for ~1.5yrs, and 7nm is just entering development at this time.

This is an industry standard approach to R&D, every IDM and foundry does it this way.

* "formally" is an official designation when a node's project team is picked and the financial commitment is outlaid and supported by the BoD. Of course there are years and years of pathfinding research that precedes an official node from being commissioned and started. Finfets for example were under "Pathfinding" at Intel for a good 6yrs before being officially transferred to the 22nm development team...so one could legitimately argue that 22nm was in R&D for 10+ yrs, but technically/officially it was only under development for 4 yrs, the finfets themselves were under research for 6yrs.

** while everyone casually refers to it as "R&D", the "R" and the "D" happen sequentially and are handled by two separate groups (and this is industry wide practice as well). At Intel the "R" happens in the so-called pathfinding phase, the "D" happens within the process node development team itself (where they make the "R" manufacturable and yieldable). At IBM the "R" is handled by various research labs such as TJ Watson whereas the "D" is handled by the process node development team at Fishkill. The "development" phase of a node is typically 4 years, the research phase can be anywhere from 2-8 yrs depending on the specific material, component, or electrical parameter under discussion.
 
Mar 9, 2013
139
0
76
You are comparing two nodes which were unavailable to any external customer, regardless the electrical parameters, for the vast majority of the time in which TSMC's 28nm has been commercially available and shipping in volumes.

Comparing Intel or GloFo to what TSMC offers is purely an academic argument if you were/are a fabless company for the past two years. Regardless what technical deficiencies you may assign to TSMC's 28nm, the bottom line is it was the only game in town for fabless companies for nearly 2 solid years.

Availability trumps inaccessible, unreliable, and inconsistent any day of the week when you are spending 2-3 yrs designing a product.



We have yet to determine what, if anything, is really afoot with Qualcomm.

But what we do know is you cannot transcend the time requirements involved in redesigning and laying out your chip (yet again) for a second foundry. There is no such thing as "hijacking" a customer at this late stage of the game.

If Qualcomm is producing chips at GloFo then Qualcomm made the decision to do so some 2 years ago (minimum) as that is the time required to port an existing vetted IC design from one foundry to another.

In the foundry business, the only time you have to intercept customers and steal them away from the competition is during the early stages of the node's development.

If GloFo wanted a customer for 2013 (like Qualcomm) then GloFo would have had to convince that customer to start designing their chips for GloFo's process flow no later than 2011.

If that is "hijacking" then it has to be the slowest darn robbery there ever has been.



The development cycle for nodes has NOT been 2 years since roughly 1992.

Node development has historically been a 4 year effort, at least for the past 20 years.

Nodes are developed in parallel. A new node is formally* started in development every 2 yrs, with two nodes perpetually in the pipeline, staggered by two years so they come to production every two years.

At Intel, for example, 14nm has been in "development**" for ~3 yrs, 10nm has been in development for ~1.5yrs, and 7nm is just entering development at this time.

This is an industry standard approach to R&D, every IDM and foundry does it this way.

* "formally" is an official designation when a node's project team is picked and the financial commitment is outlaid and supported by the BoD. Of course there are years and years of pathfinding research that precedes an official node from being commissioned and started. Finfets for example were under "Pathfinding" at Intel for a good 6yrs before being officially transferred to the 22nm development team...so one could legitimately argue that 22nm was in R&D for 10+ yrs, but technically/officially it was only under development for 4 yrs, the finfets themselves were under research for 6yrs.

** while everyone casually refers to it as "R&D", the "R" and the "D" happen sequentially and are handled by two separate groups (and this is industry wide practice as well). At Intel the "R" happens in the so-called pathfinding phase, the "D" happens within the process node development team itself (where they make the "R" manufacturable and yieldable). At IBM the "R" is handled by various research labs such as TJ Watson whereas the "D" is handled by the process node development team at Fishkill. The "development" phase of a node is typically 4 years, the research phase can be anywhere from 2-8 yrs depending on the specific material, component, or electrical parameter under discussion.

Wow! Nice info. I really didn't know anything about the process & standard industry practices before your post. I love learning something new every day.
Are you some what related to this industry?
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
Wow! Nice info. I really didn't know anything about the process & standard industry practices before your post. I love learning something new every day.
Are you some what related to this industry?

Glad to hear it :thumbsup:

Yes, am a little bit involved in the semiconductor industry, it is a very interesting area though and many people from all walks of life find themselves drawn to discussing and learning more about it
 
Mar 10, 2006
11,715
2,012
126
Glad to hear it :thumbsup:

Yes, am a little bit involved in the semiconductor industry, it is a very interesting area though and many people from all walks of life find themselves drawn to discussing and learning more about it

A "little bit" - say an individual who was in the trenches in process node development for many years!

Too modest!
 

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
We have yet to determine what, if anything, is really afoot with Qualcomm.

But what we do know is you cannot transcend the time requirements involved in redesigning and laying out your chip (yet again) for a second foundry. There is no such thing as "hijacking" a customer at this late stage of the game.

If Qualcomm is producing chips at GloFo then Qualcomm made the decision to do so some 2 years ago (minimum) as that is the time required to port an existing vetted IC design from one foundry to another.



No need of two years , actualy they switched easily due
due to ease of layout portability as well as inherent better
perfs/watt by 30 to 40% at the same 28nm node , not
counting 40% higher frequencies , that tells a lot about
TSMC process wich is firstly optimised for cost , hence
its low performances and subsequent high density.


The development cycle for nodes has NOT been 2 years since roughly 1992.

Node development has historically been a 4 year effort, at least for the past 20 years.


I was talking of using a new production node every two years.
 

sm625

Diamond Member
May 6, 2011
8,172
137
106
Assuming the A7 is approx 500 million transistors GPU and 500 million transistors non-gpu, the GPU portion would be about 40mm^2 and it would occupy about 40% of the total die. The non-gpu portion would be around 60mm^2 (50% more area per transistor, which sounds about right.) There is no way its 20nm. When apple moves to a 100mm^2 die on 20nm, it will have 1.4billion transistors or more.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
No need of two years , actualy they switched easily due
due to ease of layout portability as well as inherent better
perfs/watt by 30 to 40% at the same 28nm node , not
counting 40% higher frequencies , that tells a lot about
TSMC process wich is firstly optimised for cost , hence
its low performances and subsequent high density.

I have seen zero evidence of any of this being true in reality. If it is true then it is the industry's best kept secret because no one seems to be aware of these facts.

Do you have any supporting information that can substantiate GloFo's 28nm process provides 30-40% superior performance/watt in addition to 40% higher clockspeeds?

Marketing claims by GloFo aren't going to cut it, publications at IEDM or any other comparable peer-review public-domain venue would be sufficient though.
 

Exophase

Diamond Member
Apr 19, 2012
4,439
9
81
Samsung's process certainly never offered 40% higher clockspeeds (Cortex-A9s and A15s clocking about the same in Samsung SoCs) and nothing suggested such better perf/W. Again, this is basically taking the position that Samsung's process is similar to GF's, tell me if this is for some reason the wrong position to take.

A product made on GF's 28nm SoC optimized process materialized early this year - the SoC maker, Rockchip, mainly makes chips for extremely aggressively priced Chinese devices. They have openly lamented their struggle against smaller outfits like Allwinner who are burning through government loans while selling chips for next to nothing. As far as I'm aware, they transitioned from Chinese fabs. When the only known company who chose GF 28nm over TSMC 28nm is one desperately fighting against Allwinner it seems to suggest that it's GF who is trying to win customers on cost, not TSMC...
 
Mar 10, 2006
11,715
2,012
126
Samsung's process certainly never offered 40% higher clockspeeds (Cortex-A9s and A15s clocking about the same in Samsung SoCs) and nothing suggested such better perf/W. Again, this is basically taking the position that Samsung's process is similar to GF's, tell me if this is for some reason the wrong position to take.

A product made on GF's 28nm SoC optimized process materialized early this year - the SoC maker, Rockchip, mainly makes chips for extremely aggressively priced Chinese devices. They have openly lamented their struggle against smaller outfits like Allwinner who are burning through government loans while selling chips for next to nothing. As far as I'm aware, they transitioned from Chinese fabs. When the only known company who chose GF 28nm over TSMC 28nm is one desperately fighting against Allwinner it seems to suggest that it's GF who is trying to win customers on cost, not TSMC...

TSMC is the gold standard in the general purpose foundry world. GloFo makes a lot of noise, but they're burning through money most likely, and they're desperate to get clients on price. From murmurings I'm hearing from people in the know, GloFo is taking something in the neighborhood of 20% gross margin for their wafers.
 

Exophase

Diamond Member
Apr 19, 2012
4,439
9
81
Speaking of RK3188..

http://www.chipworks.com/TOC/Rockchip RK3188 7-16-2013.pdf

I take back anything I ever said about GF not having good density vs TSMC - this chip is very small. It's smaller than the chip currently in Apple TV, which is made on Samsung 32nm, is 36mm^2 and only has a single Cortex-A9 with 256KB of L2 cache and single core SGX543MP. This is a chip with 4 Cortex-A9s, 512KB L2 cache, and a quad core Mali-400. With naive scaling they'd be close to the same size.

I still contend that the density on Apple's A5X and A5, A5r2 chips (and probably A6 and A6X) sucks. I don't know if this problem is with Samsung or was with Apple.
 

Nothingness

Platinum Member
Jul 3, 2013
2,769
1,429
136
I still contend that the density on Apple's A5X and A5, A5r2 chips (and probably A6 and A6X) sucks. I don't know if this problem is with Samsung or was with Apple.
Could this low density be due to the use of Intrinsity Domino logic?
 

Abwx

Lifer
Apr 2, 2011
11,172
3,869
136
I have seen zero evidence of any of this being true in reality. If it is true then it is the industry's best kept secret because no one seems to be aware of these facts.

Do you have any supporting information that can substantiate GloFo's 28nm process provides 30-40% superior performance/watt in addition to 40% higher clockspeeds?

Marketing claims by GloFo aren't going to cut it, publications at IEDM or any other comparable peer-review public-domain venue would be sufficient though.

The process they intent to use is FDSOI licenced from STMicro ,
a Cortex A9 was ported to this process and fully functional chips
were tested , there s a PDF doc that relate the results with
all possible curves , freq/voltag , power/frequency and so on ,
comparing the different processes , i dont have the link since
i downoaded the doc...

A few hints :

A group of 19 European companies and academic institutions have launched a three-year, 360 million euro ($464.5 million) pilot-line project to support the industrialization of fully-depleted silicon-on-insulator (FD-SOI) technology.
................................................................................................
The FD-SOI manufacturing sources for the project are located in two fabs. The first is the pilot line in STMicroelectronics’ Crolles fab, near Grenoble, France. The dual-source is in GlobalFoundries’ fab 1 in Dresden, Germany. STMicroelectronics and IBM are the biggest proponents for FD-SOI. Not long ago, STMicroelectronics signed an FD-SOI foundry deal with GlobalFoundries.

http://semimd.com/blog/2013/05/21/group-forms-fd-soi-project/
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
The process they intent to use is FDSOI licenced from STMicro ,
a Cortex A9 was ported to this process and fully functional chips
were tested , there s a PDF doc that relate the results with
all possible curves , freq/voltag , power/frequency and so on ,
comparing the different processes , i dont have the link since
i downoaded the doc...

A few hints :



http://semimd.com/blog/2013/05/21/group-forms-fd-soi-project/

FD-SOI has little to do with GloFo. It was developed entirely outside of them, and has only recently (last 12 months) been licensed to them such that GloFo could offer it to their customers.

Claiming that GloFo is trumping TSMC because STM developed FDSOI and cross-licensed it to GloFo is not the same thing, that just means STM developed a better process flow...and so did Intel, nothing new there.

GloFo itself is still stuck with the same internal R&D problems, tied to IBM and guaranteed to lag behind TSMC by a year, if not two, at 20nm and beyond.

If GloFo's future depends on STM continuing to develop FDSOI nodes for them to cross-license then that is a dim future, nobody makes money being the middle man between two other middle men.
 

MisterMac

Senior member
Sep 16, 2011
777
0
0
FD-SOI has little to do with GloFo. It was developed entirely outside of them, and has only recently (last 12 months) been licensed to them such that GloFo could offer it to their customers.

Claiming that GloFo is trumping TSMC because STM developed FDSOI and cross-licensed it to GloFo is not the same thing, that just means STM developed a better process flow...and so did Intel, nothing new there.

GloFo itself is still stuck with the same internal R&D problems, tied to IBM and guaranteed to lag behind TSMC by a year, if not two, at 20nm and beyond.

If GloFo's future depends on STM continuing to develop FDSOI nodes for them to cross-license then that is a dim future, nobody makes money being the middle man between two other middle men.

A large part of the world's merchants might disagree with you.
Incl. WalMart

but i do agree that it seems bleak for GloFo to bet on this.
How bad is your process R&D as a Foundry - when you buy your tech\node outside ?

And in one of the most cost-sensitive markets in the world for success, geez.

It bodes bad for 2 things:

1. They do not fully believe in their own tech.
2. If it takes off - they'll have to cut revenue to the middleman.
 

piesquared

Golden Member
Oct 16, 2006
1,651
473
136
If 28nm FDSOI is running at fab 1 other processes can run at fab8 and fab2. I like the flexibility in the fab lite model. AMD can decide between a number of different nodes that best fit their products purpose and they can produce them in parallel with plenty of capacity to meet demand.
 

Revolution 11

Senior member
Jun 2, 2011
952
79
91
A large part of the world's merchants might disagree with you.
Incl. WalMart

It's not that simple. Walmart is a middleman but like most middlemen in retail markets, Walmart offers additional value both to the consumer and the manufacturer.

The manufacturer gets high volume sales, store marketing, product visibility. The consumer gets a guaranteed, screened (by Walmart's standards) product that is in a convenient location next to many other such products, allowing for easy access of goods.

GloFo offers no real advantage that TSMC does not already have. By most definitions, TSMC has better R&D, better process, better history of production. Thus, the continuing difficulties for the company.

Walmart offers certain advantages to both its consumers and partners, justifying the overhead of being a middleman entity. Glofo does not.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
A large part of the world's merchants might disagree with you.
Incl. WalMart
I didn't say the model doesn't work, I was specific in stating it would make for a dim future for GloFo.

The business of doing business in the fabless world is a tad different than the business of doing business in the retail/consumer world.

For one the commitment timeline is on the order of 2 to 4 years, and you don't make those kinds of commitments without having considerably justification for your confidence in the foundry delivering on time and in spec.

If you, as a casual retail consumer, go to Walmart and find them to be out of stock of your favorite toothbrushes or toothpaste are you screwed for the next 2 yrs like AMD was when they had to cancel Wichita and Krishna? Or do you just get in your car and drive over to the nearest Target store and buy what you need and move on with your day?

If GloFo is hinging the future of their high-performance (in relation to TSMC's high performance offerings) on the basis of expecting STM to develop it for them then that is not the type of foundry business model that leaves customer's with justification in being confident that GloFo, and STM, will actually deliver 2-4 years out.

Big difference between the two examples, which is why I wasn't making my example a sweeping generalized one, rather I was intentionally being specific about how this would play out for GloFo.
 

Sable

Golden Member
Jan 7, 2006
1,127
99
91
Always enjoy reading IDC's posts (insightful and based on actual real world experience) vs Joe Internet (made up from articles read on semi accurate and fudzilla et al).

IDC, one of the main reasons I still read these forums. Thank you.
 

anexanhume

Junior Member
Sep 14, 2013
7
0
76
Could this low density be due to the use of Intrinsity Domino logic?

That's what Jon Stokes thought back when Apple bought Intrinsity: http://arstechnica.com/apple/2010/04/apple-purchase-of-intrinsity-confirmed/

I've had someone suggest to me that they may be using m-of-n encoding in their logic too: http://www.computer.org/csdl/proceedings/async/2010/4032/00/4032a015-abs.html

Whatever the reason, Apple's design decisions for low density seem to have been deliberate. There were also allegations that issues with power consumption were complicating their transition to TSMC. Perhaps they are shifting their logic paradigm too.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
59
91
Could this low density be due to the use of Intrinsity Domino logic?

That's what Jon Stokes thought back when Apple bought Intrinsity: http://arstechnica.com/apple/2010/04/apple-purchase-of-intrinsity-confirmed/

I've had someone suggest to me that they may be using m-of-n encoding in their logic too: http://www.computer.org/csdl/proceedings/async/2010/4032/00/4032a015-abs.html

Whatever the reason, Apple's design decisions for low density seem to have been deliberate. There were also allegations that issues with power consumption were complicating their transition to TSMC. Perhaps they are shifting their logic paradigm too.

Density is way too dependent on both business and engineering decisions for anyone in the laymen's sphere to really be able to divine the "why" with any confidence.

For example, all it takes is for a project manager to be told he has 50% of the original budget to get the chip designed with...and viola', your density is gonna suck because you simply don't have the luxury of optimizing the design to be (1) high-density and (2) anything else (such as high clockspeed, low power, released to market in a short timeline, etc).

The fundamental reason all these xtor density discussions are basically red herrings comes down to the fact that xtor density is a byproduct of an entire decision tree that exists within any given company, a decision tree to which we are all blind and ignorant when it comes to the details.
 

anexanhume

Junior Member
Sep 14, 2013
7
0
76
Density is way too dependent on both business and engineering decisions for anyone in the laymen's sphere to really be able to divine the "why" with any confidence.

For example, all it takes is for a project manager to be told he has 50% of the original budget to get the chip designed with...and viola', your density is gonna suck because you simply don't have the luxury of optimizing the design to be (1) high-density and (2) anything else (such as high clockspeed, low power, released to market in a short timeline, etc).

The fundamental reason all these xtor density discussions are basically red herrings comes down to the fact that xtor density is a byproduct of an entire decision tree that exists within any given company, a decision tree to which we are all blind and ignorant when it comes to the details.

All points well taken The person who suggested m-of-n encoding to me knew many Apple engineers, which is why I didn't dismiss it in the first place.

Also, I think we can agree that while Apple may have had time budgets, there were no $ budget issues with their designs.

I think we can agree that there has been some significant internal change. Whether that's logic type with a perf/W requirement attached to it, A7 being the first true design they've all had their engineering on, etc. Something significant has changed, either in manpower/man hours spent, or some radical technology shift.
 

Exophase

Diamond Member
Apr 19, 2012
4,439
9
81
There are some other points which could link inferior density to Samsung and not just Apple when using Samsung's process:

- Exynos 4212, like A5, was a lot larger than its competitors: http://www.itproportal.com/2011/06/...-samsung-exynos-4210-soc-die-shot-comparison/
- Samsung says Cortex-A15s on their 28nm Exynos 5410 take nearly 5mm^2 each (probably including L2 cache: http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13) while extrapolation from nVidia's Tegra 4 die picture suggest < 3mm^2 each w/L2. nVidia's picture is clearly photoshopped, but it's more likely that they'd just paste stuff over low level components while keeping the same overall floorplan, rather than something completely made up.

In addition to Apple suddenly pointing out much better density after apparently moving to TSMC.

Could be that inferior density is an artifact Samsung's design tools and IP library rather than problems with the process itself. I have no idea how much Samsung still licensed Intrinsity's work after they were bought by Apple, especially for IP that's totally non-Apple like Cortex-A15 and Mali.
 

raghu78

Diamond Member
Aug 23, 2012
4,093
1,475
136
In the near term Intel's process lead is actually increasing as Intel has shown 14nm Broadwell silicon at IDF 2013 while none of the ARM chip designers have shown any 20nm product demo. also TSMC 20nm seems to be now more of a H2 2014 event with 20nm wafer revenue being high single digits (around 8%) of total revenue for 2014.

Long term definitely Intel's lead is going to reduce and eventually all companies will have to deal with the reality - the death of Moore's law.

here is a fantastic keynote by Robert Colwell (former Intel architect of Pentium Pro) . he is with DARPA as Director of Microsystems Technology office. Colwell says that according to him the death of Moore's law is at 7nm and 2020.

http://www.darpa.mil/Our_Work/MTO/Personnel/Dr_Robert_Colwell.aspx
http://en.wikipedia.org/wiki/Bob_Colwell

http://www.youtube.com/watch?v=JpgV6rCn5-g

So Intel cannot depend on their process lead forever. sooner or later Intel needs to compete on architecture, software and apps. Also Intel needs to focus on programmability too. thats where AMD with HSA are focussed. Thats the right approach.
 
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