itanium 2 with 24 mb cache?

[iwantanewcomputer]

anybody see the new article about all the amd and intel processors.

it shows an itanium in the furture with ~24 mb l3 cache and 1700 million transistors. how much would one of these cost, cause isn't cache a very expensive thing to add?

now here's some fun math, assuming this thing is 90nm, and based on the size of the prescott vs it's transistor count

112 mm / 125 mil

with 1700 mil transistors that would be a die size of 1523 mm, that's huge,

just rambling, any other opinions

 

[Vette73]

Could be a multi core chip also.

That and they need to do something as a Opteron chip that cost a fraction of the itanium is giving it a run for its money, and some.

 

[mamisano]

I too believe that this will be at least dual core, 12MB Cache per core.

 

[Gamingphreek]

Also remember that even though the Opteron competes well with the Itanium 2 the Itanium 2 is really in a completely different league. Up in the enterprise world they do need 24mb of cache well at least a lot of cache prob not 24mb.

-Kevin

 

[Vette73]

^

Yes BUT the itanium needs a lot of cache, like the P4, as it has a horriable latency and bandwisth to and from the RAM in multi-cpu setups. But the opteron, with its on die mem controller, does not need all the extra cache to compete with the itanium. Then take into account the price difference, and the opteron wins hands down overall.

 

[Accord99]

But then you take into account that people looking for extremely large systems, like the 512-way SGI Altix where CPUs account for a relatively small fraction of the price, as well as people looking for a migration path from their existing PA-RISC, Alpha and SGI MIPS based systems and then you realize comparing two marginally overlapping products to be a waste of time.

 

[Accord99]

Originally posted by: iwantanewcomputer
anybody see the new article about all the amd and intel processors.

it shows an itanium in the furture with ~24 mb l3 cache and 1700 million transistors. how much would one of these cost, cause isn't cache a very expensive thing to add?

Cache is relatively cheap because it can be made redundant and Intel has economy of scale on its side.

now here's some fun math, assuming this thing is 90nm, and based on the size of the prescott vs it's transistor count

112 mm / 125 mil

with 1700 mil transistors that would be a die size of 1523 mm, that's huge,

It should be around 600mm, cache can be much more tightly packed than logic.

 

[Dman877]

Isn't cache essentially ram running at the speed of the proc? So a P4 extreme edition has 2 mb of 3.2/3.4 ghz ram on die?

Seems to me that a proc with 24 mb of high speed cache will most likely cost 5 figures...

 

[Lyfer]

Wow, 24mb cache, must be the price of a ferrari for that chip. I remember the old days when my school got Quad Xeon 500MHZ w/4MB cache, they were about $35k each server.

 

[SickBeast]

Just out of curiousity, isn't 24MB of cache a complete waste of die space? Wouldn't they see much more performance gains from adding more FPU's, memory controllers, and integer units to the core? 24MB seems excessive. I don't even know of applications that require such capabilities.

As for cost, it should cost more than 24 Prescotts, especially considering yields. I wonder how big the die size is on these chips. *edit NM...sorry OP. *

 

[anthrax]

Originally posted by: SickBeast
Just out of curiousity, isn't 24MB of cache a complete waste of die space? Wouldn't they see much more performance gains from adding more FPU's, memory controllers, and integer units to the core? 24MB seems excessive. I don't even know of applications that require such capabilities.

As for cost, it should cost more than 24 Prescotts, especially considering yields. I wonder how big the die size is on these chips. *edit NM...sorry OP. *

24MB will be very useful for the Itanium 2........very very useful... WHY? Lets compare a typical Intel style Memory Heriachy for a Multi processor system.
With Intel XEON / ITANIUM

CPU1<==> Cache\
CPU2<==> Cache \ Front Side Bus (6.4GB) <==> Memory controller <=8.4 GB/S=> Main Memory)
CPU3<==> Cache /
CPU4<==> Cache/

With AMD Opeteron, Power5 (Please note that Hyper Transport is a Point 2 Point archecture.)

Memory<=6.4GB=> Cache <=> On die mem controller <=> CPU1 => Hyper Tranport bus (1600MB) \
Memory<=6.4GB=> Cache <=> On die mem controller <=>CPU2 => HyperTransport Bus (1600MB) / <=> I/O controller

As you can see if you have many CPU's on a Intel system, they will still be sharing the same 6.4G/B of FSB bandwidth inorder to access the Main Memory.... This of course is a bottleneck.. A large 24MB cache will significantly reduce the amount of traffic on the FSB since each processor will not have access main memory as much since more of its frequently used data can be stored in high speed cache memory.

8.4 GB is achived by using Quad channel memory controller using DDR2100 ECC. (2100 x 4)

 

[SickBeast]

Originally posted by: anthrax

Originally posted by: SickBeast
Just out of curiousity, isn't 24MB of cache a complete waste of die space? Wouldn't they see much more performance gains from adding more FPU's, memory controllers, and integer units to the core? 24MB seems excessive. I don't even know of applications that require such capabilities.

As for cost, it should cost more than 24 Prescotts, especially considering yields. I wonder how big the die size is on these chips. *edit NM...sorry OP. *

24MB will be very useful for the Itanium 2........very very useful... WHY? Lets compare a typical Intel style Memory Heriachy for a Multi processor system.
With Intel XEON / ITANIUM

CPU1<==> Cache\
CPU2<==> Cache \ Front Side Bus (6.4GB) <==> Memory controller <=8.4 GB/S=> Main Memory)
CPU3<==> Cache /
CPU4<==> Cache/

With AMD Opeteron, Power5 (Please note that Hyper Transport is a Point 2 Point archecture.)

Memory<=6.4GB=> Cache <=> On die mem controller <=> CPU1 => Hyper Tranport bus (1600MB) \
Memory<=6.4GB=> Cache <=> On die mem controller <=>CPU2 => HyperTransport Bus (1600MB) / <=> I/O controller

As you can see if you have many CPU's on a Intel system, they will still be sharing the same 6.4G/B of FSB bandwidth inorder to access the Main Memory.... This of course is a bottleneck.. A large 24MB cache will significantly reduce the amount of traffic on the FSB since each processor will not have access main memory as much since more of its frequently used data can be stored in high speed cache memory.

8.4 GB is achived by using Quad channel memory controller using DDR2100 ECC. (2100 x 4)

Thanks, that was a very informative reply.

Out of curiousity, would it not be cheaper and more efficient for intel to develop an SMP setup which is similar to what AMD does with the Opterons? 24MB of cache just seems enormous; they could probably make at least 24 Prescotts for each of these behemoths that they produce.

The strange thing is, the last benchmarks I read comparing the 800mhz FSB Xeon to the Opteron were very close. I'm guessing that in memory-intensive situations the Opterons will be much faster though, based on what you just said.

 

[IntelUser2000]

24MB is not much on the next-generation Itanium 2 with 90nm process since the current Itanium 2, which is Madison already has 6MB L3 running at 1.5GHz, and in 3-4 months or less there will be an 9MB version at 1.7GHz.

Itanium 2 Montecito(maybe Itanium 3)

-90nm process
-Up to 2.5GHz
-Dual-core
-Hyper-threading
-512KB Data, 256KB Instruction L2(or its 512KB-I, 256K-D, not sure)
-667MHz bus with a possible 256-bit interface?(current Itanium 2 has 400MHz 128-bit bus which is like 800MHz 64-bit bus used in Pentium 4)
-20% less power consumption than current Itanium 2(or the 9MB cache one)
-New connection link called "Arbiter bus" to manage the communication two cores
2-3x faster than the Madison 9MB
-Silverdale Virtualization Technology(Also inside Montecito will be the first iteration Intel?s Silverdale technology, designed to help increase the performance of existing virtualization software such as Microsoft?s Virtual Server and EMC?s VMware, which lets computer run several OSes in different partitions)

-Foxton Technology(if the processor is running lower than the thermal spec, it will overclock the processor automatically to get back to the thermal spec and such)
-Dynamic Power Management
-Pellston Technology(which shuts corrupted caches off)

Here's the latest pricing list for the Itanium 2

Processor Pricing in US$

Itanium 2 1.50GHz, 6MB L3 4227
Itanium 2 1.40GHz, 4MB L3 1980
Itanium 2 1.30GHz, 3MB L3 910
Itanium 2 1.60GHz, 3MB L3 2408
Itanium 2 1.40Ghz, 3MB L3 851
Itanium 2 1.40GHz, 1.5MB L3 851
Itanium 2 1.00GHz, 1.5MB L3 530

That's with a recent price cut. It doesn't mean though you are gonna be able to buy the 1.00GHz version at 530 dollars and assemble your system since its for high end server. Typically the official pricing for the highest end Itanium 2 is a little bit higher than the highest Xeon MP, which is ~$3600, of course the chipset and such will cost more on the Itanium than the Xeon.

I think the die will be less than 600mm2. I don't see how it is possible to manufacture a die that big. The size of the die is almost big as the Pentium M chips if its 600mm2!!

Considering Itaniums will have 9MB cache very soon, it is very logical when going to dual core hyperthreading, you should have more than twice the size.

 

[Jeff7181]

Didn't feel like reading everything, but I saw people comparing the Opteron to the Itanium 2. That's an incorrect comparison. The Opteron competes with the Xeon. AMD doesn't currently have a product that competes with the Itanium 2.

 

[Zebo]

Itanium runs what? windows? Seems like a waste of money to me unless it's to take over those enterprise sun farms.

 

[anthrax]

Having a Intergrated Memory controller has its issues... It reduced the flexibilty you have in designing a server.......

On a Processor with a ondie memory controller like the Power 5 or the AMD Opeteron. You can have only up to 4 DIMM slots per CPU....... This limits the possible memory configuration of a server......

A comparable PA-RISC or Itanium server could have upto 32 DIMM because they seperated the memory controller from the Processor.......

Other possible reason for not choosing a intergrated memory controller include..
1: Intergrating the memory controller onto a Xeon will put alot of Chip set maker out of business.

2: Intergrating a memory controller on Itanium chips will mean that HP will have add memory controllers to their line of PA-RISC processors. (these are due to be replaced by the Itanium)...... Since the Itanium was co-devloped with HP, HP probably wouldn't have liked having to add memory controllers to its soon to be retired PA-RISC line of processors. In short, don't expect Intel to add a memory controller onto the Itanium before HP pushes out its last PA-8900 processor. That is due in late 2006.

 

[Gamingphreek]

Originally posted by: Zebo
Itanium runs what? windows? Seems like a waste of money to me unless it's to take over those enterprise sun farms.

Your joking right? Well if you aren't here it is:

Itanium's run on enterprise workstations, the OS is usually Unix, or something similiar to that. Actually it is meant to compete with those sun enterpsie server farms, however Intel is not exactly the best player in that field.

Anyone know how Alpha was doing before it was bought.

-Kevin

 

[Sohcan]

Originally posted by: iwantanewcomputer
anybody see the new article about all the amd and intel processors.<BR><BR>it shows an itanium in the furture with ~24 mb l3 cache and 1700 million transistors. how much would one of these cost, cause isn't cache a very expensive thing to add?

Transistor per transistor and die area per die area, cache is much "cheaper" than core logic, from a basis of design effort, power consumption (static and dynamic), and performance ROI.

<BR><BR>now here's some fun math, assuming this thing is 90nm, and based on the size of the prescott vs it's transistor count<BR><BR>112 mm / 125 mil<BR><BR>with 1700 mil transistors that would be a die size of 1523 mm, that's huge, <BR><BR>just rambling, any other opinions

Cache has a transistor density close to 10x higher than core logic, especially for higher-levels of cache. For what it's worth, the maximum die size allowed with 90nm lithography tools is between 600 mm2 and 700 mm2 (I can't recall exactly).

Originally posted by: Dman877
Seems to me that a proc with 24 mb of high speed cache will most likely cost 5 figures...

Not at all, see the new price list in IntelUser2000's post. "Cost" and "price" are two entirely different issues...FWIW, I remember reading a Microprocessor Report article that estimated the cost of McKinley (421 mm2 1 GHz Itanium 2) to be around $125. And that chip was produced on 200mm wafers, while the upcoming 90nm Itanium will be produced on 300mm wafers at a much higher volume. In addition, Itanium 2's L3 cache architecture, which occupies much of the chip area, has a lot of redundancy built in, which, combined with the defeaturing of the L3 cache for lower-priced variants, has a large positive effect on yield. Itanium 2's core area is actually relatively small, a product of both the architecture and design methodology.

Originally posted by: Dman877
Just out of curiousity, isn't 24MB of cache a complete waste of die space? Wouldn't they see much more performance gains from adding more FPU's, memory controllers, and integer units to the core? 24MB seems excessive. I don't even know of applications that require such capabilities.

It's not like all we're doing is adding more cache...there's a HUGE host of new features going into the 90nm Itanium 2. (I might be a little defensive since I'm on the design team)

As far as the decision for the large L3 cache, it definitely is very useful for Itanium 2's target market: big databases that are many terabytes in size. For mid-range and back-end database applications, each 1/2 MB of cache adds 1% in performance. Witness IBM POWER5, which has on-die memory controllers and a huge amount of scalable bandwidth, yet still retains an (off-die) 144 MB L3 cache shared among 4 chips.

Out of curiousity, would it not be cheaper and more efficient for intel to develop an SMP setup which is similar to what AMD does with the Opterons?

I wish (off the record) that Itanium had on-chip links and memory controllers already, but there are also non-technical reasons to consider. Itanium uses custom chipsets from HP, SGI, IBM, Unisys, NEC and Bull to support single systems with up to 256 CPUs (and 512 soon from SGI). While a single Itanium 2 node uses a shared bus with up to 4 CPUs, these chipsets allow memory bandwidth to scale across multiple nodes while the number of CPUs increase. These systems were all introduced within the last year or so, and a lot of R&amp;D goes into them...we can't just start changing the system interface on a whim. So one of the unfortunate side affects of designing a common CPU used across high-end systems from many different manufacturers is that the system interface can't change quite so often.

Originally posted by: Zebo
Itanium runs what? windows?

...and HPUX, Linux, OpenVMS and NSK, and on a virtualization layer, GCOS and z/OS (Bull and IBM's mainframe OSs). And based on the rumblings from Sun, Solaris may make a return to Itanium soon.

 

[SickBeast]

Sohcan, thanks very much for such an informative reply; your posts in the CPU forum are invaluable.

I read the other day, to my surprise, that within the next few years the itanium is planned to be mainstream technology. While this sounds exciting for the end user, I'm curious about intel's direction when it comes to 64-bit. Do they view AMD64 as a temporary solution? Do they intend to make the itanium's 64-bit architecture the standard, just as x86 has been for years?

On another note, do you know off hand what the performance of these chips are like when it comes to rendering, particularly in 3D Studio Max (if it supports the itanium)? For me, this type of application is the main bottleneck slowing my productivity.

I was also reading the the itanium now performs twice as fast as the Xeon from a cost perspective. I find myself starting to become very interested in these chips whereas in the past I didn't even give them a second thought.

 

[TerryMathews]

Originally posted by: SickBeastDo they view AMD64 as a temporary solution? Do they intend to make the itanium's 64-bit architecture the standard, just as x86 has been for years?

Intel is a lot like Nintendo, circa 1994. They are top dog, but they have a very twisted perception of reality.

Intel probably views IA32e (AMD64) as a stepping stone to IA64 (Itanium). Of course, the industry isn't going to look at it that way. AMD64 is here to stay.

You'd think Intel would have learned after the RAMBUS debacle, but their ability to underestimate market realities seems to know no bounds.

 

[Sohcan]

Originally posted by: SickBeast
Sohcan, thanks very much for such an informative reply; your posts in the CPU forum are invaluable.

I read the other day, to my surprise, that within the next few years the itanium is planned to be mainstream technology. While this sounds exciting for the end user, I'm curious about intel's direction when it comes to 64-bit. Do they view AMD64 as a temporary solution? Do they intend to make the itanium's 64-bit architecture the standard, just as x86 has been for years?

"Only the paranoid survive." Intel has numerous contingency plans...more than a year or two out, the roadmap gets hazy. These are the questions only time will resolve.

On another note, do you know off hand what the performance of these chips are like when it comes to rendering, particularly in 3D Studio Max (if it supports the itanium)? For me, this type of application is the main bottleneck slowing my productivity.

I don't know about mainstream rendering apps, but Itanium 2 reportedly excels at raytracing...benchmarks with POVRay have showed Itanium 2 leading with a much greater margin than with other benchmarks.

I was also reading the the itanium now performs twice as fast as the Xeon from a cost perspective. I find myself starting to become very interested in these chips whereas in the past I didn't even give them a second thought.

The plan is for Itanium to have twice the performance of Xeon at the same system cost within the next couple of years...again, time will tell.

 

[clarkey01]

"The plan is for Itanium to have twice the performance of Xeon at the same system cost within the next couple of years...again, time will tell."


Hmmm i would have thought the cost of fabbin IA2 would be quite a bit more then Xeons on 300 mm wafers, hence why then cost more.

 

[SickBeast]

Originally posted by: Sohcan
I don't know about mainstream rendering apps, but Itanium 2 reportedly excels at raytracing...benchmarks with POVRay have showed Itanium 2 leading with a much greater margin than with other benchmarks.

Once they have a port of 3D Max or something I can easily adapt to, I'll likely switch to the itanium platform then. I would have to see benchmarks compared to Opteron, of course, but from the sounds of it IA64 is very promising for my profession. I typically have 50-100 ray traced lights in my scenes.

From what I have been told, 64-bit CPUs will have an enormous boost on 3D rendering. I just wish it would catch on already. We need Windows-64 and a large number of mainstream apps ported to 64-bit. My computer is taking over 4 hours to generate each of my rendered images, and I could even use a higher resolution if my hardware weren't so prohibitive. If a dual-cored 64-bit CPU could cut my render times down to under an hour each, it would make my life much easier.