- Mar 27, 2009
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According to Techinsights here IMFT 64L NAND is two 32L 20nm 3D NANDs string stacked.
Current IMFT "dies" for 64L are 256Gb 20nm TLC (ie, 2 x 128Gb 32L TLC string stacked), 512Gb 20nm TLC (ie, 2 x 256Gb 32L TLC string stacked) and 1024Gb 20nm QLC (ie, 2 x 512Gb 32L QLC* string stacked). This is the second generation of 3D NAND from IMFT. The first generation comprised of a single 32L die which could used as either 384Gb TLC or 256Gb MLC.
*These 32L 512Gb QLC could hypothetically also be used as 384Gb TLC or 256Gb MLC (essentially what first Gen IMFT die was or is).
Next generation of IMFT NAND (the third generation) is 96L but don't yet have specs for the die capacity.
My speculation for third Gen (3 x 32L string stacked) is the IMFT will keep the layers per die at 32, but will use 16nm lithography rather than 20nm. This will result in an increase in capacity for each 32L die from 384Gb TLC to 512Gb TLC. String stack three of these 32L 512Gb TLC dies together and it comes out to be either 96L 1536Gb TLC or 96L 2048Gb QLC. So although layers only increase 50% (comparing 3rd Gen to 2nd Gen) 3D QLC capacity per "die" increases by 2x.
So that would be the large 96L die for 3rd Gen....but next question is whether or not there will be a smaller die for 3rd Gen? I am not sure...but it would make sense there would be at least one. Maybe 3 x 32L 256Gb TLC for 96L 768Gb TLC or 96L 1024Gb QLC? (This smaller 96L 1024Gb QLC for increased parallelism (and improved yields) over the 96L 2048Gb QLC.
P.S. For fourth Gen Intel and Micron are going there separate ways but my speculation is that the base 32L die (now shrunk down to 16nm) would increase to 64L. So fourth Gen could double capacity over third Gen by increasing layers to 192L (via 3 x 64L 16nm 3D NAND string stacked).
Current IMFT "dies" for 64L are 256Gb 20nm TLC (ie, 2 x 128Gb 32L TLC string stacked), 512Gb 20nm TLC (ie, 2 x 256Gb 32L TLC string stacked) and 1024Gb 20nm QLC (ie, 2 x 512Gb 32L QLC* string stacked). This is the second generation of 3D NAND from IMFT. The first generation comprised of a single 32L die which could used as either 384Gb TLC or 256Gb MLC.
*These 32L 512Gb QLC could hypothetically also be used as 384Gb TLC or 256Gb MLC (essentially what first Gen IMFT die was or is).
Next generation of IMFT NAND (the third generation) is 96L but don't yet have specs for the die capacity.
My speculation for third Gen (3 x 32L string stacked) is the IMFT will keep the layers per die at 32, but will use 16nm lithography rather than 20nm. This will result in an increase in capacity for each 32L die from 384Gb TLC to 512Gb TLC. String stack three of these 32L 512Gb TLC dies together and it comes out to be either 96L 1536Gb TLC or 96L 2048Gb QLC. So although layers only increase 50% (comparing 3rd Gen to 2nd Gen) 3D QLC capacity per "die" increases by 2x.
So that would be the large 96L die for 3rd Gen....but next question is whether or not there will be a smaller die for 3rd Gen? I am not sure...but it would make sense there would be at least one. Maybe 3 x 32L 256Gb TLC for 96L 768Gb TLC or 96L 1024Gb QLC? (This smaller 96L 1024Gb QLC for increased parallelism (and improved yields) over the 96L 2048Gb QLC.
P.S. For fourth Gen Intel and Micron are going there separate ways but my speculation is that the base 32L die (now shrunk down to 16nm) would increase to 64L. So fourth Gen could double capacity over third Gen by increasing layers to 192L (via 3 x 64L 16nm 3D NAND string stacked).
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