Ivy Bridge is a Tick +

[ydnas7]

What makes it more than a tick?

 

[zebrax2]

Because of finfet?

Edit: Tri-gate as intel calls it

 

[Idontcare]

What makes it more than a tick?

It comes with Lyme disease?

LOL, seriously though this is the first I have officially heard/seen Intel use the term publicly but TuxDave referred to it the other day when he mentioned that Intel has gotten much more aggressive about squeezing more performance improvements out of their tick steps.

I'm going to guess that this is part of the explanation of why the dieseize for IB seemed to suggest poor shrink scaling at 22nm.

If the IB cores themselves are not simple shrinks of the existing SB cores but rather are beefier versions even still then it would explain why the die size is reduced only some 25% or thereabouts.

As to "what" the new special sauce is, exactly, that makes IB a "tick+" and have larger cores (more xtors per core than SB cores) we can safely assume there is a whole set of new ISA extensions coming, but it has to be more than that because Penryn was called a tick and it too included SSE4 extensions.

 

[Cogman]

With Intel, ticks generally mean "new architecture" tocks are "shrink that architecture and maybe improve a few things. Ivy Bridge is going to be a new architecture + a die shrink provided by the finfets.

It is interesting that they are going to do this. The whole idea behind doing the tick/tock cycle was "new architectures are hard to do, die shrinks are hard to do, so lets separate the two and get good at one then the other."

 

[ydnas7]

the gpu is much beefier, the L3 is also larger, but my bet is that the tick+, refers to the CPU core having design features that Mooly wanted to implement in SB, but the risk/timetable resulted in these features appearing in IB instead.

 

[qliveur]

With Intel, ticks generally mean "new architecture" tocks are "shrink that architecture and maybe improve a few things.

You've got it backwards. Tock is new architecture, and tick is die shrink.

I know; it makes no sense to me, either.

 

[Cogman]

You've got it backwards. Tock is new architecture, and tick is die shrink.

I know; it makes no sense to me, either.

Ah, my mistake.

 

[Idontcare]

I know; it makes no sense to me, either.

It is based on the node.

New node, tick-tock in the new node.

Next node, tick-tock.

Since process technology shrink timeline is the rate limiter...SB could have been designed 10yrs ago but would not have been remotely manufacturable on anything prior to 65nm, and not commercially viable to manufacture on anything prior to 32nm.

So the reference point for tick-tock nomenclature naturally evolved around the process nodes instead of the microarchitectures.

 

[Nemesis 1]

It comes with Lyme disease?

LOL, seriously though this is the first I have officially heard/seen Intel use the term publicly but TuxDave referred to it the other day when he mentioned that Intel has gotten much more aggressive about squeezing more performance improvements out of their tick steps.

I'm going to guess that this is part of the explanation of why the dieseize for IB seemed to suggest poor shrink scaling at 22nm.

If the IB cores themselves are not simple shrinks of the existing SB cores but rather are beefier versions even still then it would explain why the die size is reduced only some 25% or thereabouts.

As to "what" the new special sauce is, exactly, that makes IB a "tick+" and have larger cores (more xtors per core than SB cores) we can safely assume there is a whole set of new ISA extensions coming, but it has to be more than that because Penryn was called a tick and it too included SSE4 extensions.

In the 8core BD 4 core SB thread I posted 2 links , In one of those 2 links is a big hint at what you just alluded to.

 

[Riek]

It comes with Lyme disease?

LOL, seriously though this is the first I have officially heard/seen Intel use the term publicly but TuxDave referred to it the other day when he mentioned that Intel has gotten much more aggressive about squeezing more performance improvements out of their tick steps.

I'm going to guess that this is part of the explanation of why the dieseize for IB seemed to suggest poor shrink scaling at 22nm.

If the IB cores themselves are not simple shrinks of the existing SB cores but rather are beefier versions even still then it would explain why the die size is reduced only some 25% or thereabouts.

As to "what" the new special sauce is, exactly, that makes IB a "tick+" and have larger cores (more xtors per core than SB cores) we can safely assume there is a whole set of new ISA extensions coming, but it has to be more than that because Penryn was called a tick and it too included SSE4 extensions.

Well previous ticks did almost nothing to the architecture. We know for sure that ivy gpu will support dx11 and openCl right? so that seems to warant a + for me and would probably warant the additional die space.

 

[ydnas7]

the penryn tick gave

>45% performance improvements are possible in situations that are bandwidth and floating point intensive

new SMD instructions for Media / Gaming / Graphics developers

up to a 50 percent larger cache

so if IB did this. it would amount to 4 core Sandy E performance in a mainstream cpu.

 

[Edrick]

the L3 is also larger

Where did you read this?

 

[tweakboy]

But heres the big question. wow 22nm . When is 11nm coming out or 1nm ,, What happens after a 1nm process ???We done then for years to come...

 

[tweakboy]

Bring on the Xeon servers lets run those as a desktop ?

 

[Tuna-Fish]

Well, the size of a single copper atom is ~130pm (0.13nm). I don't know how close we can get to building structures from individual atoms, but I wouldn't say semiconductor scaling is done just yet.

 

[Borealis7]

i get a feeling we're going to see Perf/Watt go up the roof with these new transistors. thats what i'm hoping for anyway...

 

[AtenRa]

Theory,

IB could be an SB-E shrink + 16 EUs for the IGP and not an SB shrink,

Take the SB-E, take off two core's, keep the same Cache per core as SB-E, take off 2x 64-Bit IMC, take off some PCI-e lanes, install an IGP (16 EUs) produce it at 22nm and you could have Ivy Bridge.

That could explain the bigger die (Larger Cache than SB + 4 more EUs in the IGP) and why they call it a Tick+.

 

[ydnas7]

IB die

SB die
just looking at wafer comparison, if the core were about the same, then the L3 has increased somewhat, and the IGP has increased lots.

 

[Arachnotronic]

Take the SB-E, take off two core's, keep the same Cache per core as SB-E, take off 2x 64-Bit IMC, take off some PCI-e lanes, install an IGP (16 EUs) produce it at 22nm and you could have Ivy Bridge.

Neat theory, but probably wrong. If this were the case, it'd totally make SNB-E quad core worthless.

But then again, i7-9xx is pretty worthless thanks to i7-2600

 

[deimos3428]

IB die

Die shrink? What die shrink? That thing's huge! *runs off to buy a full tower*

 

[GammaLaser]

Well, the size of a single copper atom is ~130pm (0.13nm). I don't know how close we can get to building structures from individual atoms, but I wouldn't say semiconductor scaling is done just yet.

One of the big limiters to scaling MOSFETs has traditionally been the gate oxide thickness. For 45nm planar tech, you were looking at oxides that are only a couple of atoms thick. With such a thin oxide comes all the leakage/power issues as well.

HKMG and 3D FETs are helping to mitigate the problem and I'm not sure if the gate oxide is still the scaling limiter for 3D FETs, but it may very well be.

At some point the CMOS scaling with Si will hit another wall but Moore's Law can still continue. Higher device densities and speeds will come in the form of chip stacking/TSV technology and alternative semiconductor materials.

 

[ydnas7]

Die shrink? What die shrink? That thing's huge! *runs off to buy a full tower*

that's exactly the point, per unit area Intel has double the number of xtors, so there is a lot of extra circuitry going into the 4 core IB. A LOT of extra xtors