Theses curves take account of 32 to 22nm shrink , including
the capacitances reduction and any others parameters that
differentiate the two process.
< snip text that is irrelevant because of false premise >
The part in bold is where you are heading into left field and creating a scenario in your mind that simply has no basis in reality.
You are making assumptions that are incorrect in regards to the process parametrics captured and represented in the graph.
Look at the x-axis and y-axis labels on the graph. Notice that they read "Transistor gate delay" and "Operating Voltage".
That's it. Nothing more. Everything else that you are convoluting and contriving in your post (the stuff I snipped out of the quote) is not represented by the data that Intel is presenting in the graph.
Decreasing the operating voltage from 1V to 0.78V would be expected to reduce power-consumption by 50% if everything else was held constant (i.e. you reduced the voltage on a chip from the same node).
P = C * F * V^2
A reduction in voltage results in the following power reduction: (the i's and f's are subscripts representing initial and final respectively)
Pf/Pi = (Cf * Ff * Vf^2)/(Ci * Fi * Vi^2)
For the same chip on the
same node at the same clockspeed, Ci = Cf and Fi = Ff:
Pf/Pi = (Cf * Ff * Vf^2)/(Cf * Ff * Vi^2) = Vf^2/Vi^2
Pf/Pi = 0.78^2/1.0^2 = 0.6084/1 = 0.6084
So we'd expect the lower-voltage chip to consume only 60% of the power that the higher-voltage chip consumes when both chips are clocked the same and produced on the same node.
(And that is if we use a square relationship which has been empirically true since 90nm. If it is a cubed relationship then we get 0.78^3/1^3 = 0.4746.)
However, decreasing the operating voltage
AND shrinking the elements (a further reduction in capacitance) decreases power-consumption even further because the capacitance is
also decreasing.
Pf/Pi = (Cf * Ff * Vf^2)/(Ci * Fi * Vi^2)
For a node shrink, if the same chip were implemented in the newer node then Ci > Cf (the shrunk node results in the individual components being smaller, less surface area, less capacitance for the same layout).
Pf/Pi = (Cf * Ff * Vf^2)/(Ci * Ff * Vi^2) = (Cf * Vf^2)/(Ci * Vi^2) = (Cf/Ci) * (Vf^2/Vi^2)
= (Cf/Ci) * 0.6084
Since Ci > Cf (the capacitance of a Sandy Bridge chip on 32nm will be higher than the capacitance of the same chip if shrunk and implemented on 22nm) that means Cf/Ci < 1.
Multiplying 0.6084 by a number smaller than 1 is going to make the product
even smaller than 0.6084.
I convervatively budgeted for a mere 15% reduction in capacitance for 22nm over 32nm, a 20-30% reduction would be more the norm but I intentionally wanted to pad the numbers upwards so as to avoid the very silliness that ensued in the thread anyways.
Ugh...I just realized we've been through this before.
http://forums.anandtech.com/showpost.php?p=31502387&postcount=78
http://forums.anandtech.com/showpost.php?p=31502667&postcount=80
You know the equations, you know I know the equations, you are just trolling me at this point, we've covered all of this before.
How many more times are we going to need to bring you up to speed on the same basic equations before you stop wasting everyone's time being arrogant by calling shens and BS when you have amply demonstrated your own ignorance of these equations and have no basis for your assertions?
At any rate there is no need to take my word for it,
Intel already stated as much: (emphasis added)
Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32-nm chips.
Notice the bit about
less than half while operating at the same performance?
Doesn't that kinda square up with what I stated, computed, elucidated above?
Or would you have us believe that Intel is straight up lying about the reality of the situation as well?