Its due to the volume needed for new factories with lower process nodes to generate profit and payback the factories and node research. The ROI simply requires higher volume. For example only 2 companies can do 14nm with profit most likely. And at 10nm and down. There is only Intel. Unless something like 5-10 years between node changes is what you want.
You can already see at TSMC that they are somewhat stuck at 28nm. If you want 20nm chips you almost have to pay 2x.
A 22nm factory costs 5-6billion$, a 14nm 10billion$ plus R&D on top. Intel uses around 2billion$ a year on that alone if I recall right. 1900 Ph.Ds just to develop a new node.
So there you have it, without increasing volume, no new process nodes. With competition you got lower volume while having to compete on higher node processes with poor performance as result. And as stated above, those independent foundries like TSMC/Glofo dont work to push the nodes without too high cost increase. Not to mention those foundries produce generic processnodes and cant optimize their production line for a certain individual design. For example Intels 22nm and Haswell is designed hand in hand for one another.
Volume also dictates how much money can be spend on the actual design. And with designs getting increasingly more complex, that also affects performance. We already see it with the designs now with Intel vs AMD. This is also why we dont have 20+ x86 competitors like in the beginning. Simply no room left for them due to ROI.
While I have no doubt that Nvidia has unquestionable access to pricing info on past nodes as well as price negotiations underway on nodes under development to form the basis of their graph above - I would point out that if we are to believe the data presented in this graph then we are to believe that 40nm never brought any cost savings over 55nm in its entire history of production and that is without question not true.
The data containing such an obvious error makes me question the assumption then that 20nm will not be lower in cost than 28nm.
However, there is one way that I can rationalize the data in the graph, and that involves this graph not representing cost/transistor but instead representing TSMC's willingness to attempt to balance supply with demand while maximizing their own gross margins.
In other words the graph shows Nvidia's purchasing expenses, not TSMC's production costs, and if that is the case then any arguments to be made using this graph to support the position that the new nodes themselves are not providing cost-benefits is flawed.
In the absence of competition, TSMC will naturally gravitate to a wafer pricing model which ends up being cost-normalized at the per-transistor level while maintaining gross margins by virtue of providing benefits in the form of lower-power and higher-clocks to the customers who are seeking to make profits themselves off of the newer nodes.
Customers looking to buy 20nm wafers versus 28nm wafers are going to be looking to buy those 20nm wafers because the resultant parametric properties of the chips themselves can command a higher resell price in the market - better power consumption, better clockspeeds. And TSMC knows this, so they would be the fools to not price accordingly.
And so why would TSMC not price accordingly to what the market will bear? Note we are no longer talking about the cost to develop and produce nodes, which is what you were using the Nvidia graph to support, but rather we are now talking about TSMC's ability to set wafer pricing as they see fit for the sake of maximizing their own margins in the absence of competition from the other foundries.
TSMC gets to tell Nvidia that Nvidia won't see a cost reduction per xtor for 20nm not because there is no cost reduction to be had, but because TSMC knows that Nvidia has no other choice but to buy TSMC's 20nm wafers if Nvidia wishes to compete with AMD when AMD releases their 20nm GPU's and with Qualcomm when Qualcomm releases their 20nm ARM chips.
Nvidia's problem isn't TSMC and it isn't that new nodes are not providing cost savings benefits, it is that UMC and GloFo aren't keeping pace with TSMC in their node release schedule which leaves TSMC the option of raising wafer prices as they see fit.
And that makes the story behind the graph a very different one indeed, it has nothing to do with new node production costs at TSMC and everything to do with gross margins at TSMC.