Kabini Rumors

[Ventanni]

Honestly, I think the phrase "greater parallelism" is a pretty ambiguous term for Steamroller. AMD's focus for Steamroller outside of just doubling the decoding units is correcting many of the internal inefficiencies and streamlining the flow of data of the Bulldozer architecture, and is sure to have substantial performance improvements through more efficient use of resources.

The Bulldozer architecture is very capable of providing excellent performance....as long as they can keep it fed.

Feed the beast? lol

 

[Olikan]

@ SocketF

I still think EX core will be a BIG performance jump vs SR. Similar to BD -> SR jump, if not bigger. Also we have no clue on which process the EX core will be made.

....what we know about EX core?
i only know about HDR library :|

 

[inf64]

....what we know about EX core?
i only know about HDR library :|

A presentation from late Chuck Moore. Link. Although roadmaps change I doubt they will change the course for the EX core. It's listed as future (2018?) technically possible HPC node:

There you go, "projected" 256bit pipelines in AMD's own presentation. Note they put a disclaimer below image, standard practice for this type of "projection" of engineering capability.

 

[SocketF]

@ SocketF

I still think EX core will be a BIG performance jump vs SR. Similar to BD -> SR jump, if not bigger.

Of course you can still think and wish, but given AMD's current naming schemes (Vishera just a Bulldozer Rev. C, Richland just a better Trinity), I see the probability, that EX is just a slightly modified SR as much higher than anything else.
Two big revolutionary consecutive core architectures would be really nice, but I dont see how that could happen, especially with all the lay offs.

Also we have no clue on which process the EX core will be made.

Yes, but we know that it is planned for 2014 and that AMD only has 28nm chips on the server-roadmaps for 2014.
Ok - you never know, maybe there are changes, but GF cannot produce 20nm yet, TSMC starts in the end of 2013 with the risk production ... I'd rule 20nm out for 2014. Maybe it would be feasible for small chip, like a Kabini shrink, but not for a bigger core with Bulldozer modules.

There you go, "projected" 256bit pipelines in AMD's own presentation. Note they put a disclaimer below image, standard practice for this type of "projection" of engineering capability.

Hmm 2018 ... yes that would be possible I guess, then even GF should be able to produce chips in 16nm :ninja:
If you really hope that EX will come with 256 fmacs already in 2014 (or maybe late now in 2015) then I'll wonder what AMD would do between 2015 and 2018.

 

[Olikan]

There you go, "projected" 256bit pipelines in AMD's own presentation. Note they put a disclaimer below image, standard practice for this type of "projection" of engineering capability.

awesome! Nice find man...

i really knew nothing about amd's future chips post steamroller

 

[inf64]

I doubt EX core will launch in 2014. In early 2015 maybe and yes with expanded FP units from 2011 BD . For 4 years timeframe one would hope they thought of SIMD capability for HPC market.

 

[Idontcare]

Hmm 2018 ... yes that would be possible I guess, then even GF should be able to produce chips in 16nm :ninja:

That would be 14XM, not 16nm.

The distinction is relevant because the "XM" in 14XM stands for eXtreme Mobility. There is no "14XM for HPP or SHP".

AMD has a choice of 20nm SHP or waiting until GF's 10nm SHP arrives, they may field parts using 14XM but they would be clockspeed limited to smartphone and tablet type devices.

TSMC has 16nm all buttoned up for themselves in the HP and SHP markets. Samsung might be a competitor, if they can launch on time, otherwise it is going to be 28nm all over again.

 

[VirtualLarry]

TSMC has 16nm all buttoned up for themselves in the HP and SHP markets. Samsung might be a competitor, if they can launch on time, otherwise it is going to be 28nm all over again.

Is that a "real" 16nm? Unlike Intel's 22nm, that is really 26nm from what I've read. Compared to TSMC's 28nm, that I think was really 28nm. So Intel may not be as far ahead of TSMC as they want us to think they are.

 

[erunion]

Is that a "real" 16nm? Unlike Intel's 22nm, that is really 26nm from what I've read. Compared to TSMC's 28nm, that I think was really 28nm. So Intel may not be as far ahead of TSMC as they want us to think they are.

Nope. That must have been some ARM friendly PR blitz, as it misled by omission. If intels 22nm is really 26nm then TSMC's 28nm is really like 31nm effective gate(or was it 33nm?).

Dang, chipworks did a tear down on it but I cant find it now.

By the way, there is no real or fake nodes. Or I suppose they are all fake node, as the numbers don't represent a physical measurement.

 

[IntelUser2000]

Is that a "real" 16nm? Unlike Intel's 22nm, that is really 26nm from what I've read. Compared to TSMC's 28nm, that I think was really 28nm. So Intel may not be as far ahead of TSMC as they want us to think they are.

You can't base nodes based on specific feature sizes anymore. It's all relative nowadays.

If a 22nm process has a 26nm gate, compared to 32nm's 30nm's gate, but offers 2x density, and traditional gains in performance(30%) then it can be considered a full shrink.

If the same "next-gen" process only offers 1.3x the density gain and 10% gains in performance, you wouldn't call that full node gain regardless of what they claim in "gate sizes" or whatever.

So metrics aren't so straightforward nowadays. It's like basing solely clock speeds or cores on power. Real CPUs are lot more complicated than that.

 

[SocketF]

I doubt EX core will launch in 2014. In early 2015 maybe

Well it was labeled "2014" on the early roadmap that I posted. Since then 20nm SHP is history and Kaveri/Steamroller is late for half a year. So yes, maybe 2015, but still then there are 3 years until 2018 where AMD should not innovate the FPU.
As I said previously, I doubt it very much, but lets wait and see. After Kaveri we'll hopefully get some info about Bulldozer 4.0 (=EX), too.

That would be 14XM, not 16nm.

The distinction is relevant because the "XM" in 14XM stands for eXtreme Mobility. There is no "14XM for HPP or SHP".

Ah yes, sorry, just remembered that the 16nm are probably the "real" size, but the "XM" is important, too, will call it 14XM from now on again (if I dont forget it ^^).
There is still the FD-SOI chance, the next node should be 14nm, but of course there are still no details. Neither if GF will manufacture it nor if AMD will use it. But there is a possibility.

Is that a "real" 16nm? Unlike Intel's 22nm, that is really 26nm from what I've read. Compared to TSMC's 28nm, that I think was really 28nm. So Intel may not be as far ahead of TSMC as they want us to think they are.

TSMC has the best / real numbers, we discussed them a few days back.

 

[mrmt]

Feel free to ask questions based on those old posts here (or start a new thread if the mods prefer) so we don't resurrect ancient threads. If I'm using terms anyone doesn't understand in some of those posts I can translate... I had written some of the posts more for other industry people rather than for the layperson.

I took some time to read your posts, took some time reading about some concepts that are out of my real of knowledge (RTL, some blocks in the processor), and the conclusion I got is that there is a huge business case for P&R tools (I also got to the conclusion that I'd not be a good CPU engineer ). You can get a smaller, less complex team developing a processor in a smaller time frame and even getting more area efficient.

I cannot but feel a sense of awe for Intel R&D teams. To be able to afford, and more important, be able to manage such a big, complex team and still deliver targets on schedule. Perhaps some of the Intel insiders here could tell a bit on how Intel manage things to still get hand-designed chips of such a quality, but maybe this is one of the blue vs red opinions that every career track has.

It seems that synthesis design was one of the few good management decisions that Ruiz took on his term. Had he stuck with hand design, he would probably deliver some A64 improvement, which would be a good thing, but this would be the last hurrah of the R&D department because AMD wouldn't be able to afford the next generation as it grew more complex. I also left with the impression that whatever faults Bulldozer has, it isn't synthesis fault. To say the truth I find rather strange a design with lots of blank space using a method that tends to fill every blank space available on the die.

Before being through your posts I had a sense that bobcat was a huge lost opportunity for AMD, because they had a nice chip but didn't improve enough on it. Now I'm sure they lost a huge opportunity, maybe the opportunity of their lives. Because the chip could be improved in a much faster and flexible manner, and instead they threw everything and the chair on Bulldozer.

I can see why Rory Read is so keen on Jaguar, and why he once said that Brazos was "beautiful". If they have a project where they can improve in a faster, flexible way it is Jaguar, and having in mind that it was designed with low cost in mind, it is exactly what AMD needs to safeguard their remaining margins on current markets and fight for new ones. A nice add-on would be if it received a crash low power consumption treatment, akin to Clovertrail.

But as it is now, if Intel prices the 22nm Atom low enough, and if it pans out correctly, then what would be good margins will become not-so-good margins on the consumer market, so AMD will be completely dependent on getting enough embedded/semi-custom revenues to survive.

 

[inf64]

I cannot but feel a sense of awe for Intel R&D teams. To be able to afford, and more important, be able to manage such a big, complex team and still deliver targets on schedule. Perhaps some of the Intel insiders here could tell a bit on how Intel manage things to still get hand-designed chips of such a quality, but maybe this is one of the blue vs red opinions that every career track has.

You are surprised how they can do it? A small hint: billions of dollars invested in tools and personnel. That's how they did it in the past. Let's see them continue this crazy investment plan in the next couple of years.

 

[R0H1T]

You are surprised how they can do it? A small hint: billions of dollars invested in tools and personnel. That's how they did it in the past. Let's see them continue this crazy investment plan in the next couple of years.

If I had to guess the next die shrunk products won't arrive till fall, at the earliest, or could even be delayed till the next holiday season. As was the case with Apple, this free ride's over for Intel & they'd do well to compete with ARM vendors on an equal footing let alone overtake them in the medium to long term !

 

[mrmt]

You are surprised how they can do it? A small hint: billions of dollars invested in tools and personnel. That's how they did it in the past. Let's see them continue this crazy investment plan in the next couple of years.

Yes, I'm awed. Maybe because I too work for a multi-billion company and I have a glimpse of how complex it is to structure and manage big, complex teams for a multi-billion project.

It isn't just a question of throwing money at the problem, because money can buy you a lot of things but cannot put the right managers in the right place, and the right team leaders with the right engineers and make all those people walk in the same direction and talk the same language. Doing this requires a lot of efforts, a lot of human effort. It isn't something you can shop around.

The human dimension of those big projects is often overlooked, but it is the single most important element for the success of the project. You can do a lot of things to make up for resource deficiencies, including using P&R tools to make up for a smaller team, but give the guys deficient leadership and these guys will not achieve anything except a huge bill to foot.

 

[ThePeasant]

Thanks for the read CTho. :thumbsup:

 

[Abwx]

It isn't just a question of throwing money at the problem, because money can buy you a lot of things but cannot put the right managers in the right place, and the right team leaders with the right engineers and make all those people walk in the same direction and talk the same language. Doing this requires a lot of efforts, a lot of human effort. It isn't something you can shop around.

And when all this doesnt work , well , throw a lot of money
to bribe the whole market...

That s just a matter of money , the rest is corporate mythology...

 

[Khato]

TSMC has the best / real numbers, we discussed them a few days back.

What discussion was this precisely? Because the only one I recall had TSMC in the same boat as Intel with respect to SRAM size scaling and behind in terms of transistor performance.

You can find the majority of the interesting information on this lovely chart from Real Word Technologies (I keep hoping they'll have an updated version at some point) - http://www.realworldtech.com/iedm-2010/7/ The SRAM cell sizes can easily be found elsewhere, but the Idsat per Ioff numbers for both NMOS and PMOS transistors are annoying to find otherwise. Note that Intel's transistors consistently out-perform those of TSMC - comparing the 45nm nodes against one another and Intel's 32nm versus TSMC's 28nm Intel has a 10-20% lead in NMOS drive current and 40% in PMOS. It's an important distinction seeing as how such would mean that designs using TSMC's process would need to use larger than minimum size transistors in order to match Intel's performance.

As for SRAM cell size scaling, if we go all the way back to the 90nm node they're reasonably comparable - 1.0um^2 for Intel and 0.99um^2 for TSMC. Then it's simple algebra to determine the process 'size' of one node relative to another based on SRAM cell sizes (note that when I state relative to another process node I'm treating that node as if it actually was exactly the designated size since that's the standard industry practice.)

Intel
90 - 1.0
65 - .57 - 68nm relative to 90
45 - .346 - 51nm relative to 65, 53nm relative to 90
32 - .171 - 32nm relative to 45, 36nm relative to 65, 37nm relative to 90
22 - .092 - 23nm relative to 32, 23nm relative to 45, 26nm relative to 65, 27nm relative to 90


TSMC
90 - .99
65 - .499 - 64nm relative to 90
45 - .296 - 50nm relative to 65, 49nm relative to 90
40 - .242 - 41nm relative to 45, 45nm relative to 65, 44nm relative to 90
28 - .130 - 29nm relative to 40, 30nm relative to 45, 33nm relative to 65, 33nm relative to 90
20 - .081 - 22nm relative to 28, 23nm relative to 40, 24nm relative to 45, 26nm relative to 65, 26nm relative to 90

That broader picture tells an interesting story. Namely that TSMC definitely scaled better on the 65nm and 45nm processes than Intel, but since then they've been slipping. To the point where Intel's 22nm and TSMC's 20nm are basically back on the same scale. Combine that with the fact that TSMC's transistor performance is inferior and how exactly do they have the "best / real numbers"?

 

[SocketF]

Feel free to ask questions based on those old posts here (or start a new thread if the mods prefer) so we don't resurrect ancient threads. If I'm using terms anyone doesn't understand in some of those posts I can translate... I had written some of the posts more for other industry people rather than for the layperson.

Ok I would have a question, even thread related:

Can you please explain what "core macro" means here? I totally have no clue, what that could be. I mean I know what a "macro" in general is, but in that context of chip design? I searched the thread for "macro" and there were no hits, so I hope the question was not answered before.

thanks a lot

SF

Edit:
@Khato:
I meant with "numbers" only the credibility to the mentioned gate length. Nothing else. As VirtualLarry mentioned Intel's 22nm process in reality has 26nm. So I thought he is asking about gate lengths and nothing else. Yes Intel may have better electrical characteristics but I didnt expect them to be the context here.

 

[Exophase]

When you're doing hardware design you'll have some library of macros that you can incorporate into your design. Like a macro for a FIFO, an adder, a multiplier, a full ALU, or a full CPU core. It's basically some block with some defined interface that has already been designed and can be reused.

This can come in soft (pre-synthesis, RTL level) or hard-form (something you put down straight on a circuit floorplan, may have been custom laid out). AMD is probably referring to hard macros that have custom layouts optimized for the process. The idea that these are the only macros used in Jaguar's design would imply that the rest of it is straight RTL (like VHDL or Verilog) that can be synthesized.

This link might help with the distinction:

http://digitalelectronics.blogspot.com/2008/01/soft-macro-vs-hard-macro.html

(also CTho9305 can and probably will give a better answer ;p)

 

[sequoia464]

A nice add-on would be if it received a crash low power consumption treatment, akin to Clovertrail.

But as it is now, if Intel prices the 22nm Atom low enough, and if it pans out correctly, then what would be good margins will become not-so-good margins on the consumer market, so AMD will be completely dependent on getting enough embedded/semi-custom revenues to survive.

As always I appreciate your posts, I do have a question though. Do you know what the power requirements for Temash will be? I thought they were supposed to be competative power wise with clovertrail?

 

[Khato]

Edit:
@Khato:
I meant with "numbers" only the credibility to the mentioned gate length. Nothing else. As VirtualLarry mentioned Intel's 22nm process in reality has 26nm. So I thought he is asking about gate lengths and nothing else. Yes Intel may have better electrical characteristics but I didnt expect them to be the context here.

Yeah, I was tempted to quote that post as well but didn't quite get around to it. After all, sure, Intel's 22nm process is closer to 26 or 27nm... and by the same metric TSMC's 28nm process is really something around 33nm. Hence my confusion as to how TSMC can be considered to have the best / real numbers when they're every bit as skewed.

 

[mrmt]

As always I appreciate your posts, I do have a question though. Do you know what the power requirements for Temash will be? I thought they were supposed to be competative power wise with clovertrail?

Temash will have stronger performance than Clovertrail but higher power consumption too. Clovertrail scales all the way down to phones, while Temash will be limited to tablets.

 

[AtenRa]

I don’t know if this has been shown before,

It does confirm 128 Radeon Cores and most probable 64bit memory

AMD Kabini(Jaguar Quad Core) die picture

AMD Ontario(BobCat Dual Core) Die Picture

 

[CHADBOGA]

Yeah, I was tempted to quote that post as well but didn't quite get around to it. After all, sure, Intel's 22nm process is closer to 26 or 27nm... and by the same metric TSMC's 28nm process is really something around 33nm. Hence my confusion as to how TSMC can be considered to have the best / real numbers when they're every bit as skewed.

As they are not Intel, they just have to be better.