I'm skeptical. The L1 (64KB) + L2 (2MB) icache miss rate has got to be real close to zero for most applications. If your real hot code exceeds 2MB (or even 1MB with two uncorrelated programs) then you're probably running something very weird. Furthermore, they'd have to then fit in L3.
I looked around for NB overclocking tests, found this:
http://www.rage3d.com/reviews/cpu/amd_fx_8150/index.php?p=8
Maybe you have others? The big problem with this comparison is that the OC2 tests don't just involve a 9% northbridge overclock but a 50% increase in DRAM clock speed. Which is reflected directly in Sandra's synthetic memory bandwidth test.
Checked my sources again, most of them were unfortunately Phenom X6s. But a print magazine tested NB-OC with a Vishera under starcraft2, they measured +7% with a 20% OC from 2,0 -> 2,4. Not that great as I thought, but still not bad.
The thing is, if you're bandwidth bound to main memory you're not going to see an improvement just by increasing core to L3 bandwidth.
Depends how many threads/cores you have. Check the sandra scores of the FM2 CPUs with 2 modules. They are far below the maximal DDR3 bandwidth for dual channel configurations. Hence there is another limitation, which has to be the NB, there is nothing else between memory controller and module.
Did you happen to see the leaked PS4 diagrams that reference Onion and Garlic (and "Onion+") buses? Could be that an evolution of the design made it into Kabini.. or could have been specific for Sony's needs.
Not sure, but the stuff I saw were no leaks, just some self made diagrams, if I remember correctly.
Is that 6T / 3 module info official or just guess?
It is semi-offical. BSN leaked some AMD PDFs about Kaveri and there it says "2 to 3 modules". There is a low chance that it is fake, but it seems legit, thus semi-official ;-)
SHP doesn't necessarily mean PD-SOI,
TSMC's doesn't. SHP is whatever process GF wants to affix that label to.
Yes, but GF already has lots of 28nm processes, they even changed the High performance process from HP to HPP (high performance plus), seems the parameters of TSMC's version was better, so they adjusted a few of them.
I cannot think about anything else than SOI for a "SHP"-version, and traditionally SHP always has been PD-SOI since they use it.
To my knowledge though IBM had zero interests in developing an SOI-based half-node for the fab club. It may surface again at 20nm, but I'm 99% confident it isn't in the mix for 28nm.
That however is a good argument ... I couldnt find anything else about 28nm SOI either, but I found an 22nm SOI process from IBM:
http://www.chipworks.com/blog/technologyblog/2012/12/19/ibm-surprises-with-22nm-details-at-iedm/
The strange thing is: It is still gate-first.
How big are the chances, that GF will call that thing 28SHP? If they are zero, how big are the chances that GF did the job alone? Impossible?
Well then I also have no clue, then we would be back to the inital question about the meaning of SHP.
We made all kinds of high-clock high-power ICs. In fact we made three versions of every node, pretty similar to how any foundry operates.
SOI doesn't mean "high clocks that are otherwise unattainable without the use of SOI", it means "high clocks with less R&D effort to get those high clocks versus the R&D involved in getting the same clocks with bulk-Si".
Oh, didnt know both of that, thanks
I really thought SOI can achive more performance, I think I red some time ago that SOI is 20% better (in some parameter, drive strength or whatever it was, no clue now), and thus delivers a better clock-headroom.
Its the same story as with leakage. SOI makes the process node development easier because it cuts out a bunch of engineering legwork. But it transfers the work over to the accounting dept as well as the design team. Their jobs become all the more difficult, and it only pays off if your wafer volumes fall below a certain threshold.
Yes totally clear then, if there is no performance advantage the calculation is rather easy.
Provided you are a small enough player then using SOI as a crutch for getting your node developed will actually pay off in the end.
But if you are a high volume player (and what foundry doesn't intend to be?) then the savings in R&D turn into unacceptable production costs in the fab.
Yes .. then the only reason would be financial. SOI is like paying less in the beginning (e.g. getting a loan), but then you have to pay off interest to SOITEC over the years = indefinitely.
Haven't you ever noticed the lack of interest in SOI by all the large volume fab owners? It was only ever seriously considered by the small-volume guys (AMD included). That was for economic, not technical performance, reasons.
Sure I did, but I thought it is just like a Pepsi <> Coke thing, furthermore I thought the engineers at IBM are great people, so they shouldn't choose sth bad.
But now it makes more sense with your example .. IBM's server chips are low-volume, so it is very likely better for them. Even if they would be above the threshold, they could just price the CPUs higher (but I think PPCs are already expensive enough :biggrin: ). AMD however is in a price fight with intel and has to sell a big and probably expensive 315mm² die with low ASPs ... a bad situation, no a really bad situation ...
No wonder that they stopped payments for the SHP20 node .. it doesnt pay off. From this point of view the switch to bulk is/was natural since GF became independent and more customers are bringing higher volume into the fab. I just hope there still will be other customers at 28nm besides the Chinese and AMD *G*
Thanks for all the information!