Kaveri Steamroller vs BulldozerPiledriver

[csbin]

http://amdfx.blogspot.com/

 

[Fox5]

http://amdfx.blogspot.com/

What's with the huge loss on floating point?

 

[erunion]

1.8 GHz? Why?

Why compare to FX not Richland?

 

[csbin]

What's with the huge loss on floating point?

L3 cache:ninja:

 

[Exophase]

1.8GHz would be typical, engineering samples used in pre-launch benchmarks are usually well below shipping clock speeds.

This is Cosmology@Home, the benchmark is BOINC which uses Dhrystone for integer and Whetstone for floating point. Both are about as useless as you get, and neither should be impacted by a lack of L3 cache since their working set fits entirely in L1 cache. The numbers are pretty meaningless. I remember there were BOINC integer numbers floating around for Bobcat before release, that showed that its IPC was nearly double that of the Atoms at the time. While the real world number was certainly much higher than Atom it was pretty much never that much higher.

Still, I wouldn't write this off as completely meaningless, if true.. a 34% increase in throughput even for a bunch of nearly meaningless integer ops has to mean something for a uarch advancement. This could be enabled by the increased decoder width more than anything else.

 

[Enigmoid]

So this shows there was no gain from bulldozer to Piledriver. Not convinced on the authenticity of the benchmark.

I'm unconvinced on the sandra benchmarks. This guy is also pulling random BS numbers out of his ass or sandra is horrible (looking at second post on that page).

On the sandra page for video bandwidth you see anything from 44GB/sec for HD 4000 to 1.5 GB/sec.

Im getting 18 GB/sec on sandra's video memory test (SP3)

 

[bgt]

http://amdfx.blogspot.com/

Nice find. Kaveri looks really promising.

 

[mrmt]

Wasn't this guy making stuff up few months ago?

 

[podspi]

What's with the huge loss on floating point?

I don't know whether this leak is legit or not (though I'm shocked we haven't had more leaks if the NDA lift really is about a month off) -- but it makes sense. With AMD apparently going all-in APU, all their CPUs now have a huge coprocessor hanging off the side. It makes sense, and I've been expecting (and still expect them to, unless they change strategies) to start depreciating the FPU.

It makes a lot of sense. If you already have a huge GPU attached to your CPU that can be used for FP, and integer performance determines most consumer's experiences, dedicate your xtor budget to the integer pipeline, not the FPU.

As people have been noting for quite some time, there are issues with this strategy, but this is the strategy AMD has telegraphed for years. That doesn't of course, mean this leak is legit

 

[NTMBK]

Wasn't this guy making stuff up few months ago?

Yup. "Simulated benchmarks". Not sure why anyone takes this joke of a blog seriously, it feels like it's written by Galego.

 

[Idontcare]

I don't know whether this leak is legit or not (though I'm shocked we haven't had more leaks if the NDA lift really is about a month off) -- but it makes sense. With AMD apparently going all-in APU, all their CPUs now have a huge coprocessor hanging off the side. It makes sense, and I've been expecting (and still expect them to, unless they change strategies) to start depreciating the FPU.

It makes a lot of sense. If you already have a huge GPU attached to your CPU that can be used for FP, and integer performance determines most consumer's experiences, dedicate your xtor budget to the integer pipeline, not the FPU.

As people have been noting for quite some time, there are issues with this strategy, but this is the strategy AMD has telegraphed for years. That doesn't of course, mean this leak is legit

It makes sense to stop investing in advancing the state of the art in your existing FPU microarchitecture...it doesn't make sense to actually invest money in developing an even lower performing one.

 

[sm625]

Of all of these unsubstantiated benchmarks, what I think is most important is the supposed 15.0 GB/s memory bandwidth. If this is really double the 6800K, then it is going to be pretty fast. I wish I knew how much of that increase comes from the RAM speed vs controller optimizations.

 

[inf64]

Disregard the supposed leaks. Until we see a benchmark from a system that at least has an image of the chip with a CPUz snapshot, all these leaks are dubious at best.

 

[Idontcare]

Yup. "Simulated benchmarks". Not sure why anyone takes this joke of a blog seriously, it feels like it's written by Galego.

It is, isn't it. Wasn't that galego's blog that he kept pimping here before he was politely asked to vacate the premises?

 

[NTMBK]

It is, isn't it. Wasn't that galego's blog that he kept pimping here before he was politely asked to vacate the premises?

Hah, that would explain it. Can we get this thread closed for being based on info from a banned member?

 

[Abwx]

http://wccftech.com/amd-kaveri-stea...oint-results-show-viable-competition-haswell/

 

[Abwx]

Hah, that would explain it. Can we get this thread closed for being based on info from a banned member?

The source is here :

http://www.chinadiy.com.cn/html/21/n-11921.html

Sorry to burst your wishes of this thread being closed
because of your flawed assumptions...

 

[mikk]

The source is here :

http://www.chinadiy.com.cn/html/21/n-11921.html

Sorry to burst your wishes of this thread being closed
because of your flawed assumptions...

They link to http://news.mydrivers.com as source. news.mydrivers is just a copy and paste page. Your argumentation is flawed.

 

[fixbsod]

My first thoughts -- where's the large gain from bd --> pd?? Nullifies the validity of this test.

So this shows there was no gain from bulldozer to Piledriver. Not convinced on the authenticity of the benchmark.

 

[Abwx]

They link to http://news.mydrivers.com as source. news.mydrivers is just a copy and paste page. Your argumentation is flawed.

Still more relevant than the one using the fact that
it s posted in Galego s site as a prove of fake ,
that the link i gave is linked to another site doesnt
prove in any way that it s a fake...

Seems that the supposed perfs are what make
some people wish that it s fake...

 

[Pilum]

It makes sense to stop investing in advancing the state of the art in your existing FPU microarchitecture...it doesn't make sense to actually invest money in developing an even lower performing one.

It can make sense if you have a fixed transistor budget and want to optimize your design for certain performance target points.

It's well known that the SR FPU will be reduced from 4 pipelines to 3 - that's been on every SR block diagram AMD ever published. It seems they used the transistor savings from that to improve integer execution. If this core was supposed to go into high-performance workstation CPUs, this would be a bad tradeoff. For a core which will see use mainly in HTPC, low-end gaming and micro-servers, this is a very good tradeoff in my opinion.

 

[Sweepr]

Seems that the supposed perfs are what make
some people wish that it s fake...

Intel cores have surpassed this kind of integer performance (per clock) for years now, and even with a 30% IPC boost (MT shall see bigger gains than plain ST due to reduced CMT penalty) it would still lag behind 2-year old Vishera FX6xxx (some models) and FX8xxx in many MT apps, dont forget there are only 2M/4C models. Not to mention FP performance got worse according to this leak and PD is pretty much equal to BD clock per clock. Yeah, sounds reliable.

 

[NTMBK]

Seems that the supposed perfs are what make
some people wish that it s fake...

The fact that the results make no sense and come from a dubious source is what makes me think it is fake. I'd love to see AMD make an excellent comeback, but getting excited over nonsense doesn't help anyone.

 

[Abwx]

Intel cores have surpassed this kind of integer performance (per clock) for years now, and even with a 30% IPC boost it would still lag behind 2-year old Vishera FX6xxx (some models) and FX8xxx in many MT apps, dont forget there are only 2M/4C models. Not to mention FP performance got worse according to this leak and PD is pretty much equal to BD clock per clock. Yeah, sounds reliable.

We ll see in a month or so....

 

[Exophase]

Erm, just because galego linked this blog all the time doesn't mean he's the author.

I don't know whether this leak is legit or not (though I'm shocked we haven't had more leaks if the NDA lift really is about a month off) -- but it makes sense. With AMD apparently going all-in APU, all their CPUs now have a huge coprocessor hanging off the side. It makes sense, and I've been expecting (and still expect them to, unless they change strategies) to start depreciating the FPU.

It makes a lot of sense. If you already have a huge GPU attached to your CPU that can be used for FP, and integer performance determines most consumer's experiences, dedicate your xtor budget to the integer pipeline, not the FPU.

As people have been noting for quite some time, there are issues with this strategy, but this is the strategy AMD has telegraphed for years. That doesn't of course, mean this leak is legit

There's two big things I think even AMD won't be disregarding so soon:

1) The part of CPUs that people call "the FPU" also includes wide integer execution capabilities, and it's better at it than GPUs are if you can use small data types.
2) Not all vector code, FP or otherwise, is well suited for GPU execution. There isn't a nice divide between your usual scalar code and full-bore GPU style compute. There are many levels in between. This gap could reduce gradually in the future but there's no way AMD is anywhere there with Kaveri.

IMO, it's a mistake to go backwards in performance on a PC part in any area where it impacts current software used in any real capacity. AMD had to have realized this with the first BD release.