Larrabee will be massive?

[Nemesis 1]

TSMC can call it 40nm. If they so choose . But its actually larger than Intels 45nm. transitor size. . Intel could release parts at both 45nm and 32nm . for larrabee. Thats what I would do if I was Intel . release a 45nm. Mid low end and a 32nm.high end Part.

At this point in the game I would think the shrink to 32nm . Would be priority over LarrabeeII. Larrabbee is a modular design. I believe its 8 core to a module. Maybe I miss understood that part . In Intels early papers it said 10 cores but I believe that was cut back to 8 cores. Connected by smaller ringbus. Each group of 8 cores has its own mini ringbus that inturn is connected to the main ring bus for communications,ect ect ect.

 

[bunnyfubbles]

Obvious trolling flamebait aside, the point still stands; 45nm - no matter the company - will be long since obsolete by 2011. Either Larrabee will be coming out before 2011 or it will be on a process smaller than 45nm (or it won't come out at all).

 

[Idontcare]

Originally posted by: Snooper

Originally posted by: IdontcareChips that sell for $10k don't have enough margins to be fabbed at >900mm^2.

Your joking, right? With 300mm wafer costs (in HVM) at or below the $3,000/wafer range, do you REALLY think they can't make money on a device above 900mm^2?

Assuming 80% utilization of the silicon (varies depending on die size, shape, major flat or notch, etc), you should be able to get right at 100 die on there. Heck, if they can only hit 50% die yield, you are still talking about 50 good die per wafer.

Now, even if this IS a $300 die (I REALLY doubt it), then you are looking at 50 * $300 = $15,000 PER wafer! More than likely, you are looking at a die cost of around $60 per good die. Through in another $60 for the rest of the card and another $60 for profit (perhaps a bit low), you are looking at a possible $180 mid range card with the performance of today's top of the line single GPU card. Not bad. ESPECIALLY for Intel.

The whole margin thing on uber expensive die comes in when you are only building a few lots of wafers at a time. If I only expect to sell 10,000 chips and I can get 50 good die per wafer and I am making 25 wafers in a lot, you are talking about a run of only EIGHT lots to make all the die I expect to need for this high price project. That leads to the simple problem that you never hit HVM, so you never get the bugs worked out. Your die yields generally are in the trash, so you have to make a lot more wafers to make up for it and that costs money.

I don't joke about the things I have personal experience with.

You seem to be indicating my experience doesn't support extension to this specific situation...alright then, its not implausible so let's entertain the scenario.

Perhaps you can tell me the die-size of the largest consumer-grade (non-military app) CMOS integrated circuit?

Naturally I'd like ASP and GM data to go with it, but let's just first get across the bridge of "you are joking, right?" commentary by you providing an example of ANY >900mm^2 IC sold in the consumer sector for <$10k.

 

[Scali]

What I think is missing in Snooper's story is the inherent imperfections in the wafer.
The larger the chip, the larger the chance of imperfections ruining the chip.
So basically, the larger your chip, the lower your yields. Taking it to the extreme, it's virtually impossible to have an entire wafer with no imperfections. Hence it's virtually impossible to build a chip the size of an entire wafer.

If all chips in a wafer would work, then I would agree with his story, then it wouldn't be all that expensive to produce large chips. But I don't think that's the case.

 

[SunnyD]

Originally posted by: bunnyfubbles
Obvious trolling flamebait aside, the point still stands; 45nm - no matter the company - will be long since obsolete by 2011. Either Larrabee will be coming out before 2011 or it will be on a process smaller than 45nm (or it won't come out at all).

Considering Intel still uses both 65nm and 90nm for their discrete logic... I wouldn't go saying 45nm will be obsolete by 2011.

 

[Idontcare]

Originally posted by: Scali
What I think is missing in Snooper's story is the inherent imperfections in the wafer.
The larger the chip, the larger the chance of imperfections ruining the chip.
So basically, the larger your chip, the lower your yields. Taking it to the extreme, it's virtually impossible to have an entire wafer with no imperfections. Hence it's virtually impossible to build a chip the size of an entire wafer.

If all chips in a wafer would work, then I would agree with his story, then it wouldn't be all that expensive to produce large chips. But I don't think that's the case.

To put it differently, reality comprehends reality pretty well...and the reality is that large die (>600mm^2) are only made for markets that can support the four digit ASP's that are necessary for the gross margins to work out as needed to provide the financial motivation it takes to pursue creating such large IC's.

Why is this the reality? Because of the reality in the fab (defects, yields, etc), the reality in the boardroom (gross margin targets, ROI, timeline to product release, risk to all of the above, etc), and the reality in the consumer markets relating to demographics and marketsize supporting any specific pricing tier.

What is lacking from Snooper's story is the reality part. But yeah, if we ignore that aspect of it, then, well yeah I suppose the spirit of my post does become a joke at that point.

 

[Kuzi]

Originally posted by: SunnyD

Originally posted by: bunnyfubbles
Obvious trolling flamebait aside, the point still stands; 45nm - no matter the company - will be long since obsolete by 2011. Either Larrabee will be coming out before 2011 or it will be on a process smaller than 45nm (or it won't come out at all).

Considering Intel still uses both 65nm and 90nm for their discrete logic... I wouldn't go saying 45nm will be obsolete by 2011.

45nm surely won't be obsolete by 2011, but an Intel "graphics chip" based on a 45nm process (in 2011) would not look good against 28nm offerings from AMD and NVidia

 

[Nemesis 1]

Originally posted by: bunnyfubbles
Obvious trolling flamebait aside, the point still stands; 45nm - no matter the company - will be long since obsolete by 2011. Either Larrabee will be coming out before 2011 or it will be on a process smaller than 45nm (or it won't come out at all).

I seen none. Only trueth. We argue debate this till were blue in face. Won't change what intel releasese in 1st. qt 2010. I will surely bring back this thread so we can see who had a true grasp of info that is available. We can pick and choose what we believe the question is why we choose what we choose. AMD came out with nice little duel core. I have a duel core intel running in here with me doing Benchies I rather like it alot.

 

[uclaLabrat]

Slightly OT: Does anyone have a good (read: well reasoned) speculation as to when the physical limits of Si will limit the chip size? The Si-Si bond is roughly 0.2 nm, so a 20 nm process will have features about 100 atoms thick. How long can they sustain these node shrinks?

 

[Idontcare]

Originally posted by: uclaLabrat
Slightly OT: Does anyone have a good (read: well reasoned) speculation as to when the physical limits of Si will limit the chip size? The Si-Si bond is roughly 0.2 nm, so a 20 nm process will have features about 100 atoms thick. How long can they sustain these node shrinks?

5nm is the generally accepted physical limits of scaling silicon-based CMOS.

After that more exotic material components such as CNT's (carbon nanotubes) are viewed as extending the scaling further to 1.2nm.

http://www.semiconductor.net/a...o_Limit_to_Scaling.php

The issue isn't materials science or technology, but rather it is cost. You need a product that generates enough revenue to cover the cost of developing the ever smaller and smaller nodes.

 

[Scali]

Originally posted by: Idontcare
The issue isn't materials science or technology, but rather it is cost. You need a product that generates enough revenue to cover the cost of developing the ever smaller and smaller nodes.

I wonder if it's necessarily bad if we can't go beyind 5 nm silicon. Research would just have to move to a different focus. More attention will need to be paid to getting the most out of every transistor, and multi-chip technologies will have to become more efficient. If the manufacturing process is no longer a variable, but a constant, other developments may be faster.

 

[bunnyfubbles]

Originally posted by: Kuzi

Originally posted by: SunnyD

Originally posted by: bunnyfubbles
Obvious trolling flamebait aside, the point still stands; 45nm - no matter the company - will be long since obsolete by 2011. Either Larrabee will be coming out before 2011 or it will be on a process smaller than 45nm (or it won't come out at all).

Considering Intel still uses both 65nm and 90nm for their discrete logic... I wouldn't go saying 45nm will be obsolete by 2011.

45nm surely won't be obsolete by 2011, but an Intel "graphics chip" based on a 45nm process (in 2011) would not look good against 28nm offerings from AMD and NVidia

which is entirely my point

 

[Nemesis 1]

Originally posted by: Idontcare

Originally posted by: uclaLabrat
Slightly OT: Does anyone have a good (read: well reasoned) speculation as to when the physical limits of Si will limit the chip size? The Si-Si bond is roughly 0.2 nm, so a 20 nm process will have features about 100 atoms thick. How long can they sustain these node shrinks?

5nm is the generally accepted physical limits of scaling silicon-based CMOS.

After that more exotic material components such as CNT's (carbon nanotubes) are viewed as extending the scaling further to 1.2nm.

http://www.semiconductor.net/a...o_Limit_to_Scaling.php

The issue isn't materials science or technology, but rather it is cost. You need a product that generates enough revenue to cover the cost of developing the ever smaller and smaller nodes.

I have good imagination. But when you guys talk on scale of this size . I really struggle with comprending how the circuit is completed . Just amazes me .

 

[Viditor]

Originally posted by: Snooper

Originally posted by: IdontcareChips that sell for $10k don't have enough margins to be fabbed at >900mm^2.

Assuming 80% utilization of the silicon (varies depending on die size, shape, major flat or notch, etc), you should be able to get right at 100 die on there. Heck, if they can only hit 50% die yield, you are still talking about 50 good die per wafer.

Not to pile on, but your math is off as well...
1. @971mm2 dice, that is a max theoretical 57 dice on 300mm. Or 45 after an 80% yield...
2. @650mm2 dice, that is a max theoretical 89 dice on 300mm. Or 71 after an 80% yield...

Then of course there's the costs of the mask set, equipment, electricity, packaging, testing, etc...
IDC's estimate sounds about right to me...

Put it another way...
1. Call it ~$70 in wafer expense per chip
2. Mask sets costs what, $1-2Mil?
3. Engineers salaries for the 2-3 months it takes to make a finished wafer
4. All of the other expenses (packaging, handling, testing, etc...) call it another $3k/wafer or $70/chip?

With so few actual chips coming from the wafer, payback on your investment would be a longshot indeed...

 

[Nemesis 1]

Your not piling on at all Viditor . Just to add some info .

http://www.anandtech.com/cpuch...howdoc.aspx?i=3367&p=6


Remember the design experiment? Intel was able to fit a 10-core Larrabee into the space of a Core 2 Duo die. Given the specs of the Core 2 Duo Intel used (4MB L2 cache), it appears to be a 65nm Conroe/Merom based Core 2 Duo - with a 143 mm^2 die size.

At 143 mm^2, Intel could fit 10 Larrabee-like cores so let's double that. Now we're at 286mm^2 (still smaller than GT200 and about the size of AMD's RV770) and 20-cores. Double that once more and we've got 40-cores and have a 572mm^2 die, virtually the same size as NVIDIA's GT200 but on a 65nm process.

The move to 45nm could scale as well as 50%, but chances are we'll see something closer to 60 - 70% of the die size simply by moving to 45nm (which is the node that Larrabee will be built on). Our 40-core Larrabee is now at ~370mm^2 on 45nm. If Intel wanted to push for a NVIDIA-like die size we could easily see a 64-core Larrabee at launch for the high end, with 24 or 32-core versions aiming at the mainstream. Update: One thing we did not consider here is power limitations. So while Intel may be able to produce a 64-core Larrabee with a GT200-like die-size, such a chip may exceed physical power limitations. It's far more likely that we'll see something in the 16 - 32 core range at 45nm due to power constraints rather than die size constraints.
This is all purely speculation but it's a discussion that was worth having publicly.

 

[Idontcare]

Originally posted by: Nemesis 1
Our 40-core Larrabee is now at ~370mm^2 on 45nm. If Intel wanted to push for a NVIDIA-like die size we could easily see a 64-core Larrabee at launch for the high end, with 24 or 32-core versions aiming at the mainstream. Update: One thing we did not consider here is power limitations. So while Intel may be able to produce a 64-core Larrabee with a GT200-like die-size, such a chip may exceed physical power limitations. It's far more likely that we'll see something in the 16 - 32 core range at 45nm due to power constraints rather than die size constraints.
This is all purely speculation but it's a discussion that was worth having publicly.

Yeah I expect the 32core Larrabee to fit into sub-400mm^2 die on 45nm, with the 64core variant being the 680mm^2 monstor shown by Otellini at IDF.

?The size of the product is within expectations. It is a multi-core device. What you saw on that wafer was the high-end version of it. There are obviously other versions of it that have far fewer cores for different price points. So, what you saw is the extreme version,? Mr. Otellini explained.

http://www.xbitlabs.com/news/v...rds_in_Early_2010.html

It's semi-amusing to me that this topic (core-count vs. diesize for Larrabee) seems to be recycling at a rate of about once every two weeks :laugh: Sigh, only 8 more months of it to go I suppose